Alignment mark configuration

Details Alignment mark configuration Alignment mark configuration

2006-06-06

2006-06-06

Lee, Eugene (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

Reexamination Certificate

active

07057299

ABSTRACT:
An alignment mark configuration, wherein the alignment mark is protected from being damaged from the subsequent planarization process, is described. The alignment mark configuration comprises a plurality of recesses and a flat spacing between the recesses on the substrate. If the substrate further comprises a trench structure, the spacing between the trench structure and the alignment mark is at least 5 times the flat spacing between the neighboring recesses of the alignment mark.

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