Alignment mark and method for manufacturing a semiconductor...

Details Alignment mark and method for manufacturing a semiconductor... Alignment mark and method for manufacturing a semiconductor...

2004-06-22

2008-03-04

Thai, Luan (Department: 2891)

Semiconductor device manufacturing: process

Semiconductor substrate dicing

Having specified scribe region structure

C438S401000, C438S975000, C257S797000, C257SE23179

Reexamination Certificate

active

07338885

ABSTRACT:
In a method for manufacturing a semiconductor device having an alignment mark, a buffer layer is formed on a substrate. A trench is formed at an isolation region of the substrate. The trench is filled with an insulating layer. An alignment groove is formed on the insulating layer in a scribe lane region of the substrate. The buffer layer is removed to form an alignment pattern. An alignment mark includes the alignment pattern and the alignment groove. Therefore, the alignment pattern may be not attacked by solutions in a successive cleaning process such that the alignment mark may be not damaged and maintains its original shape.

REFERENCES:
patent: 5369050 (1994-11-01), Kawai
patent: 6706610 (2004-03-01), Yoshimura et al.
patent: 6809002 (2004-10-01), Yabe et al.
patent: 2002/0063304 (2002-05-01), Toeda et al.
patent: 2002/0182821 (2002-12-01), Yabe et al.
patent: 01/67509 (2001-09-01), None

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