Air voids underneath metal lines to reduce parasitic capacitance

Details Air voids underneath metal lines to reduce parasitic capacitance Air voids underneath metal lines to reduce parasitic capacitance

1997-12-15

1999-09-14

Quach, T. N.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438622, 438669, 438739, H01L 2128, H01L 21302

Patent

active

059536250

ABSTRACT:
A method for fabricating metal lines in multilevel VLSI semiconductor integrated circuit devices is provided so as to reduce parasitic capacitance. An undercutting etching step is performed so as to form trenches underneath the metal lines for accommodating air voids, followed by forming an intra-layer dielectric between the metal lines and into the trenches so as to form air voids underneath the metal lines. As a result, the parasitic capacitance will be decreased.

REFERENCES:
patent: 5308440 (1994-05-01), Chino et al.
patent: 5310700 (1994-05-01), Lien et al.
patent: 5319237 (1994-06-01), Legros
patent: 5453154 (1995-09-01), Thomas et al.
patent: 5814555 (1998-09-01), Bandyopadhyay et al.

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