Air gap under on-chip passive device

Details Air gap under on-chip passive device Air gap under on-chip passive device

2007-01-24

2010-02-16

Chen, Kin-Chan (Department: 1792)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S702000

Reexamination Certificate

active

07662722

ABSTRACT:
A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric (“ILD”) layers are formed to overlie the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer, where the second ILD layer is resistant to attack by a first etchant which attacks the first ILD layer. A passive device is formed to overlie at least the first ILD layer. Using the first etchant, a portion of the first ILD layer in registration with the passive device is removed to form an air gap which underlies the passive device in registration with the passive device.

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