AGP/DDR interfaces for full swing and reduced swing (SSTL) signa

Details AGP/DDR interfaces for full swing and reduced swing (SSTL) signa AGP/DDR interfaces for full swing and reduced swing (SSTL) signa

1998-04-08

1999-12-21

Tokar, Michael

Electronic digital logic circuitry

Interface

Logic level shifting

326 38, 326 96, 326 86, H03K 190175

Patent

active

060054123

ABSTRACT:
An I/O interface includes latches, clocks, and conditioning circuits implemented in a custom physical layout to produce a reliable and flexible interface to high frequency busses running a plurality of protocols and signal specifications. Three clock trees are used to synchronize the buffering and conditioning of input/output signals before sending such signals to a pad or core. The clock trees are implemented via custom layouts to allow tight control of clock/strobe parameters (e.g., skew, duty cycle, rise/fall times). Two of the clock trees are local to the I/O interface and trigger a plurality of output latches configured on-the-fly to buffer output data signals from the core in asynchronous or synchronous mode. In the synchronous mode, a clock/strobe could be either edge-centered or window-strobe with respect to the data. The third clock tree distributes clock/strobes from an external source and is used to trigger a plurality of input latches configured on-the-fly to buffer input data from the pad in either a window-strobe mode or an edge-centered mode. The I/O interface also includes conditioning circuits that condition the I/O signals to be compliant with AGP/DDR protocols, as well as, full swing, reduced swing (SSTL), and TTL signal specifications.

REFERENCES:
patent: 5017813 (1991-05-01), Galbraith et al.
patent: 5530379 (1996-06-01), Konishi et al.
patent: 5646553 (1997-07-01), Mitchell et al.
patent: 5736867 (1998-04-01), Keiser et al.
patent: 5804987 (1998-09-01), Ogawa et al.

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