Method for testing a memory device

Details Method for testing a memory device Method for testing a memory device

1994-07-19

1995-07-11

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

365200, G11C 1606

Patent

active

054327458

ABSTRACT:
A method for testing a memory device including (M.times.N) bit lines having memory cells connected thereto, the (M.times.N) bit lines being divided into N bit line groups, each having M bit lines. The memory device also including a voltage supply; N first switches connected in common; N first control lines that control the N first switches; (M.times.N) second switches, wherein M second switches are provided to each of the N bit line groups; and M second control lines that control the (M.times.N) second switches. The method includes a first step of supplying N signals to the N first control lines so that all of the N first switches are conductive, and supplying M signals to the M second control lines so that the second switch that is connected to a defective bit line and any additional second switches controlled by the second control line that is common to the second switch are non-conductive while all remaining second switches are conductive; and a second step of supplying N signals to the N first control lines so that the first switch that is connected via the second switch to the defective bit line is non-conductive while all remaining first switches are conductive, and supplying M signals to the M second control lines so that the second switch and the additional second switches that are controlled by the second control line that is common to the second switch are conductive while all remaining second switches are non-conductive.

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Proceedings of The 1989 International Test Conference, "Design For Test of MBIT DRAMs", R. Kraus et al., Aug. 29, 1989, pp. 316-321.
European Search Report of Application No. EP 91 91 7343 mailed Mar. 7, 1994.
International Search Report of PCT/JP91/01323 mailed Jan. 14, 1992.

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