After gate fabrication of field effect transistor having...

Details After gate fabrication of field effect transistor having... After gate fabrication of field effect transistor having...

2007-03-30

2009-02-03

Pham, Thanhha (Department: 2894)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S154000, C257SE21632

Reexamination Certificate

active

07485519

ABSTRACT:
A field effect transistor (“FET”) is formed to include a stress in a channel region of an active semiconductor region of an SOI substrate. A gate is formed to overlie the active semiconductor region, after which a sacrificial stressed layer is formed which overlies the gate and the active semiconductor region. Then, the SOI substrate is heated to cause a flowable dielectric material in a buried dielectric layer of the SOI substrate to soften and reflow. As a result of the reflowing, the sacrificial stressed layer induces stress in a channel region of the active semiconductor region underlying the gate. A source region and a drain region are formed in the active semiconductor region, desirably after removing the sacrificial stressed layer.

REFERENCES:
patent: 7135724 (2006-11-01), Chen et al.
patent: 7198995 (2007-04-01), Chidambarrao et al.
patent: 7247534 (2007-07-01), Chidambarrao et al.
patent: 2005/0064646 (2005-03-01), Chidambarrao et al.
patent: 2006/0011984 (2006-01-01), Currie

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