Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-03
2001-06-05
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S682000, C438S683000
Reexamination Certificate
active
06242312
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a process used to create a low resistance, metal silicide layer, on a polysilicon structure.
(2) Description of Prior Art
The use of polycide, (metal silicide—polysilicon), gate structures, has resulted in a decrease in word line resistance, for sub-micron, metal oxide semiconductor field effect transistors, (MOSFET), devices, when compared to word lines fabricated using only polysilicon. One version of a polycide layer, used for gate structures, has been a titanium silicide polysilicon gate structure. The ability to selectively form titanium silicide, on polysilicon lines: via deposition of a titanium layer;, annealing to convert the portions of the titanium layer, overlying silicon regions, to titanium silicide; and removing the portions of unreacted titanium; have made titanium silicide an attractive refractory silicide, for use in a polycide gate structure. However as micro-miniaturization, or the use of sub-quarter features, proceeds, conventional procedures, used to create titanium silicide, polycide gate structures, do not allow the needed titanium silicide sheet resistance to be obtained. For example, conventional procedures, comprised of titanium deposition, anneal, removal of unreacted titanium, result in the desired sheet resistance, for polycide gate structures, with widths greater than 0.20 micrometers. However when polycide gate structures, with widths less than 0.20 micrometers are used, the resulting titanium silicide sheet resistance does not satisfy the designed, or desired, word line resistance.
This invention will describe a process for fabricating a titanium silicide layer, in which the resistance of the metal silicide layer is reduced as a result of the unique set of processing steps used. A pre-amorphization, ion implantation procedure, is first used, prior to titanium deposition, to prepare the exposed silicon surfaces, such as the exposed polysilicon, of the gate structure, as well as the exposed, heavily doped, source/drain regions, for the titanium deposition, and subsequent anneal. The pre-amorphization step, retards the movement of silicon atoms, into the forming titanium silicide layer, during the anneal cycle, thus allowing a less silicon rich, and lower resistance, titanium silicide layer to be formed. A second procedure, used in combination with the pre-amorphization ion implantation step, is an ion mixing, or an ion implantation procedure, performed after titanium deposition, but prior to the anneal procedure used to form the metal silicide layer. This procedure places the implanted species, in the titanium layer, near the source/drain interface, again retarding the movement of silicon atoms into the titanium silicide layer, during the anneal procedure, but more importantly retarding movement of boron, if a P type, MOSFET device is used, into the titanium silicide layer. Prior art, such as Anjum et al, in U.S. Pat. No. 5,401,674, describes an ion implantation procedure, into titanium, prior to the anneal, but does not describe the combination of the pre-amorphization, ion implantation, pre-titanium, and the post-titanium, ion mixing, ion implantation procedure.
SUMMARY OF THE INVENTION
It is an object of this invention to form a low resistance, titanium silicide layer, for use as a component for narrow, less than 0.20 micrometer width, polycide word lines.
It is another object of this invention to perform a pre-amorphization, ion implantation procedure, prior to titanium deposition.
It is still another object of this invention to perform an ion mixing procedure, via ion implantation into the titanium layer, prior to the anneal procedure, used to form titanium silicide.
In accordance with the present invention, a process is described for forming a low resistance, titanium silicide layer, for a narrow width, polycide gate structure, via a combination of pre-titanium, and post-titanium, ion implantation procedures. After creation of: a narrow width, polysilicon line; a lightly doped source/drain region; insulator spacers on the sides of the narrow width, polysilicon line; and a heavily doped source/drain region; a pre-amorphization, ion implantation procedure is performed, to exposed polysilicon and silicon regions, using germanium or arsenic ions. After deposition of a titanium, or titanium nitride layer, an ion mixing, ion implantation procedure is used to place germanium or silicon ions, in the titanium, or titanium nitride—titanium layer, near the metal—silicon interface. A first anneal procedure, converts titanium , overlying silicon or polysilicon, to a first phase titanium silicide layer, while titanium overlying insulator layers, remain unreacted. After selective removal of the unreacted titanium, a second anneal is used to convert the first titanium silicide phase, to a more conductive second titanium silicide phase, resulting in a narrow width, polycide gate structure, featuring low word line resistance as a result of forming the low resistance, titanium silicide layer, using the combination of ion implantation procedures, described above.
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Hsiue Hong-Che
Hu Ding-Dar
Huang Yuan-Chang
Wang Chao-Ray
Ackerman Stephen B.
Lindsay Jr. Walter L.
Niebling John F.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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