Advanced multilayer dielectric cap with improved mechanical...

Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate

Reexamination Certificate

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C257S635000, C257S758000, C257SE21277, C257SE21576, C257SE23161

Reexamination Certificate

active

07737052

ABSTRACT:
A dielectric cap, interconnect structure containing the same and related methods are disclosed. The inventive dielectric cap includes a multilayered dielectric material stack wherein at least one layer of the stack has good oxidation resistance, Cu diffusion and/or substantially higher mechanical stability during a post-deposition curing treatment, and including Si—N bonds at the interface of a conductive material such as, for example, Cu. The dielectric cap exhibits a high compressive stress and high modulus and is still remain compressive stress under post-deposition curing treatments for, for example: copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.

REFERENCES:
patent: 7091137 (2006-08-01), Lee et al.
patent: 7138717 (2006-11-01), Wang et al.
patent: 7151315 (2006-12-01), Wu et al.
patent: 7189658 (2007-03-01), Lakshmanan et al.
patent: 7514317 (2009-04-01), Lindsay
U.S. Appl. No. 10/047,968, entitled “Integration scheme for advanced BEOL metallization including low-k cap layer and method thereof,” First Named Inventor: Stephen Gates, filed on Jan. 15, 2002.

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