Advanced fabrication technique to form ultra thin gate...

Details Advanced fabrication technique to form ultra thin gate... Advanced fabrication technique to form ultra thin gate...

1998-08-05

2003-03-11

Lee, Eddie (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S591000, C438S775000, C438S783000, C257S324000, C257S411000

Reexamination Certificate

active

06531364

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to an improved transistor and a method for forming an improved transistor having an ultra thin, high K value, gate dielectric.
2. Description of the Related Art
Fabrication of a metal oxide semiconductor field-effect transistor (MOSFET) device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline silicon (“polysilicon”) material over a relatively thin gate oxide. The polysilicon material and the gate oxide are then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor serves to self-align impurities forwarded into the substrate on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant species. If the impurity dopant species used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET (“n-channel”) transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET (“p-channel”) transistor device. Integrated circuits use either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. The combination of an n-channel and a p-channel device on a single substrate is termed a complementary MOS (“CMOS”) device.
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to reduce the transistor threshold voltage, V
T
. Several factors contribute to V
T
, one of which is the gate-to-substrate capacitance. V
T
of a transistor decreases as the gate-to-substrate capacitance increases. The capacitance per unit area, C
ox
, of a gate dielectric can be expressed as:
C
ox
=∈/t
ox
where ∈ is the permittivity the gate oxide and t
ox
is the thickness of the gate oxide. The above equation for C
ox
demonstrates that the capacitance between two layers of conductive material separated by a dielectric is directly proportional to the permittivity of the dielectric and inversely proportional to the thickness of the dielectric.
By normalizing the permittivity, ∈, of a material to the permittivity of vacuum, ∈
o
, the relative permittivity of a material can be determined. Relative permittivity, or dielectric constant, K, is typically used in place of permittivity. The dielectric constant of a material is defined as:
K=∈/∈
o
Silicon dioxide (“oxide”) has a relatively low K of approximately 3.7 to 3.8. Consequently, the minimum value of V
T
, and thus the transistor switching speed, is limited by the need to maintain a certain gate oxide thickness in order to promote capacitive coupling between the gate conductor and the substrate.
Because of the relationship between gate oxide thickness and threshold voltage, conventional transistors typically include an ultra thin gate oxide to increase the gate-to-substrate capacitance, and thereby lower V
T
. The value of the gate-to-source voltage, V
GS
, required to invert the channel underneath the gate conductor such that a drive current, I
D
, flows between the source and drain regions of the transistor is decreased. Consequently, the switching speed (from off to on and vice versa) of the logic gates of an integrated circuit employing such transistors is faster, allowing the integrated circuit to quickly transition between logic states (i.e., operate at high frequencies).
Unfortunately, thin oxide films may break down when subjected to an electric field. Particularly, for a gate oxide that is less than 50 Å thick, it is probable that when V
GS
is equivalent to only 3V, electrons can pass through the gate oxide by what is known as the quantum mechanical tunneling effect. In this manner, a tunneling current may undesirably form between the semiconductor substrate and the gate conductor, adversely affecting the operability of the device. It is postulated that these electrons may become entrapped within the gate oxide by, e.g., dangling bonds. Consequently, a net negative charge density may form in the gate oxide. As the trapped charge accumulates with time, V
T
may shift from its design specification. Breakdown of the gate oxide may also occur at even lower values of V
GS
because of defects in the gate oxide. Such defects are unfortunately prevalent in relatively thin gate oxides. For example, a thin gate oxide often contains pinholes and/or localized voids due to the unevenness at which the oxide grows on a less than perfect silicon lattice. Low breakdown voltages also correlate with high defect density near the surface of the substrate.
In addition, the gate electrode is typically made from deposited polysilicon (as stated above). To lower the resistivity of the polysilicon gate, and thus increase the speed of the transistor, it is desirable that the entire polysilicon layer forming the gate be substantially doped. During a conventional transistor formation process, the polysilicon gate is typically doped at the same time as the source/drain areas in order to make the process more efficient. This simultaneous implantation may cause difficulties since the implant depth required for the gate is typically deeper than the desired implant depth of the source/drain areas. Moreover, dopants residing in the gate conductor may eventually traverse the gate dielectric and enter the channel region, causing threshold skew. In particular, the boron commonly used to dope p+ gates readily migrates though a thin gate oxide (less than 125 angstroms) under high temperature processes (e.g., annealing at 900° C.). In order to avoid this migration, processing temperatures must be lowered. Such lowering, however, may result in insufficient distribution and/or anneal of implanted dopants.
In order to resolve the problems described above, the use of a high-quality gate dielectric (i.e., one that is resistant to breakdown, has a high K value, etc.) is desired. High K value materials, such as silicon nitride (“nitride”), are sometimes used as the gate dielectric. Since nitride has a K value of about 8, a gate dielectric composed of nitride can be made thicker than a gate oxide while maintaining the equivalent gate-to-substrate capacitance. The increased thickness of a nitride gate dielectric relative to a similarly performing gate oxide helps to make the nitride gate dielectric more resistant to breakdown. Also, nitride is relatively impermeable to foreign species such as oxygen, and therefore provides an effective barrier against diffusion.
There are numerous problems, however, with many conventional techniques for implementing nitride gate dielectrics. Because of the mechanical stresses that develop at the silicon/silicon nitride interface, it is generally disadvantageous to deposit nitride directly upon a silicon wafer. Moreover, many methods of nitride deposition result in the formation of a nitride layer that is uneven, nonstoichiometric, and filled with pinholes. Such a nitride layer might contain, among other things, diffusion pathways through which dopants and electrons may undesirably pass.
Therefore, it would be desirable to develop a technique for fabricating a transistor composed of a high-quality gate dielectric. A high-quality gate dielectric would afford increased gate-to-substrate capacitance while being substantially resistant to breakdown. The improved technique would be one that avoids the problems of very thin oxides, yet provides high-speed operation necessary for modem integrated circuits. Tunneling currents formed between the gate dielectric and the gate conductor would be minimized along with the possibility of electrons becoming trapped within the gate dielectric. Migration of dopants from the gate electrode into the channel region would be substantially reduced over a conventional gate oxide. The transistor would thus be substantially resistant to threshold skews from the desired value of V
T
.
SUMMARY OF

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