Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-07-26
2005-07-26
Pham, Hoai (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S391000
Reexamination Certificate
active
06921948
ABSTRACT:
A method is provided for processing a semiconductor topography. In particular, a method is provided for decreasing the threshold voltage magnitude of a first transistor being formed within the substrate while simultaneously increasing the threshold voltage magnitude of a second transistor being formed within the substrate. In some embodiments, a width of the first transistor may be larger than a width of the second transistor. In addition or alternatively, the method may include performing a first implantation corresponding to a threshold voltage magnitude above a desired value for the first transistor. The method may further include performing a second implantation to simultaneously lower the threshold voltage magnitude of the first transistor and raise a threshold voltage magnitude of the second transistor. In some embodiments, the method may include introducing dopants of a first conductivity type into a first transistor channel dopant region and a second transistor channel dopant region simultaneously.
REFERENCES:
patent: 5989949 (1999-11-01), Kim et al.
patent: 6043128 (2000-03-01), Kamiya
patent: 6090652 (2000-07-01), Kim
patent: 6228697 (2001-05-01), Furukawa et al.
patent: 6462385 (2002-10-01), Kumagai
Cypress Semiconductor Corp.
Lettang Mollie E.
Pham Hoai
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