Adjusting a digital delay function of a data memory unit

Details Adjusting a digital delay function of a data memory unit Adjusting a digital delay function of a data memory unit

2011-04-26

2011-04-26

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189120, C365S233100, C365S233110

Reexamination Certificate

active

07933156

ABSTRACT:
An apparatus for adjustment of a digital delay function of a data memory unit comprising said data memory unit (102), an elastic store register, ESR, (104) and read clock and write clock adapted to control read and write operations, a write counter associated with the write clock and a read counter associated with the read clock. Said memory (102) works in series with said ESR (104). The memory (102) delivers two data elements from two logically neighbouring cells. Said ESR (104) writes the two data elements from the memory (102) at every cycle of the write clock, wherein if the write counter is increased by one at a cycle of the write clock the output position in the memory (102) is not changed, and if the write counter is increased by two at one cycle of the write clock the output position in the memory (102) is moved backward by one data element and if the write counter is not changed at one cycle of the write clock the output position in the memory (102) is moved forward by one data element.

REFERENCES:
patent: 6125157 (2000-09-01), Donnelly et al.
patent: 7519746 (2009-04-01), Shiraishi
patent: 2003/0012320 (2003-01-01), Bell

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