Adjustable memory self-timing circuit

Details Adjustable memory self-timing circuit Adjustable memory self-timing circuit

2001-10-31

2003-09-09

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S194000, C365S233100

Reexamination Certificate

active

06618309

ABSTRACT:

FIELD OF THE INVENTION
The invention generally relates to static random-access memory (RAM), and more specifically, to adjusting the sense timing of such a device.
BACKGROUND ART
Random access memory (RAM) contains multiple individual memory cells. Each memory cell can hold a digital bit, a zero or a one. Writing to memory corresponds to putting bits into specific memory cells. Reading from memory corresponds to finding out which bits are in specific memory cells. To save power and support high system speeds, such reading and writing should take as little time as possible.
FIG. 1
shows various functional elements of a typical RAM according to the prior art such as that described in U.S. Pat. No. 5,132,931, incorporated herein by reference. Memory cells
10
store digital bits. These cells are organized into an array of rows and columns. For ease of discussion, we will generally speak of reading the contents of such memory cells
10
. Writing into memory is similar for our purposes, and controlled by activating a write enable line. Memory cells
10
are normally grouped into horizontal rows and vertical columns of multiple cells.
Memory cells
10
are often accessed according to their row. The memory cells
10
in a particular row are accessed by activating the wordline enable signal
103
from a wordline driver
11
for that row. The contents (1 or 0) of a memory cell
10
are available at complementary (opposite) outputs, bit
101
and bitb
102
. Activating a memory cell
10
causes a voltage drop on one of its outputs, bit
101
or bitb
102
, depending on whether a zero or one is stored in the cell. The bit
101
and bitb
102
outputs for the memory cells
10
in a given column propagate along respective bit lines to a column transfer cell
12
. The column transfer cell
12
transfers the individual bit signals to parallel bit buses dio
104
and diob
105
, which are monitored by a sensing amplifier
13
. When enabled by a sense enable signal
106
, the sensing amplifier
13
senses the voltage difference between the bit buses dio
104
and diob
105
, which represent the contents of an activated memory cell
10
. If the voltage difference exceeds a threshold voltage, the data output line
108
of the sensing amplifier
13
provides a proper standard voltage-level logic signal representing a “1”. If the voltage difference is below the threshold voltage, the data output line
108
provides a proper standard voltage-level logic signal representing a “0”.
The drop in output voltage from an activated memory cell
10
occurs relatively slowly. The sense enable signal
106
should be optimally timed to enable the sensing amplifier
13
to perform the threshold comparison. If the sense enable signal
106
is too fast, the threshold comparison will occur before the bit voltages are a reliable indication of the contents of the activated memory cell
10
. If the sense enable signal
106
is too slow, operating speed is reduced and power is wasted.
Typically, a sense timing control circuit
14
produces the sense enable signal
106
. The timing of the sense enable signal
106
is determined by monitoring a column of timing cells
15
. The wordline enable signal
103
that activates a memory cell
10
also is provided to the column of timing cells
15
. Locating the column of timing cells
15
at the far end of columns of memory cells
10
can ensure that any signal propagation delays are automatically accounted for. Bit and bitb outputs from the timing cells
15
are provided to the timing control circuit
14
, which monitors the changing voltages to determine when to produce the sense enable signal
106
. The number of timing cells
15
in the column determines how fast the sense enable signal
106
is produced. A higher number of timing cells
15
means a faster sense enable signal
106
, and a lower number of timing cells
15
means a slower sense enable signal
106
.
Previously, design engineers would use computer simulations to predict the number of timing cells
15
that should be used. Then, during testing, it might be necessary to change the number of timing cells
15
in order to optimize performance. But changing the number of timing cells
15
requires that the chip mask be changed.
SUMMARY OF THE INVENTION
A representative embodiment of the present invention enables changing the number of timing cells in a static RAM during testing, without changing the chip mask. A sense enable circuit for a static Random Access Memory (RAM) includes a user-determinable number of timing cells. The timing cells are enabled by a wordline enable input to produce a timing bit line output. A sense timing control circuit is triggered by the timing bit line output and produces a sense enable signal. The sense enable signal enables a sensing amplifier to read the logic state of memory cells in communication with the sensing amplifier.
In a further embodiment, an external control circuit produces a control output to allow a user to determine the number of timing cells. For example, fuses may be used to control the number of timing cells. In one specific embodiment, the external control circuit produces three control outputs so that the user-determinable number of timing cells is a range of up to eight. In another embodiment, the external control circuit produces four control outputs so that the user-determinable number of timing cells is a range of up to sixteen.


REFERENCES:
patent: 5132931 (1992-07-01), Koker
patent: 5245584 (1993-09-01), Zampaglione et al.
patent: 5963074 (1999-10-01), Arkin
patent: 5999482 (1999-12-01), Kornachuk et al.
patent: 6046951 (2000-04-01), El Hajji
patent: 6172925 (2001-01-01), Bloker
patent: 6229746 (2001-05-01), Tooher
patent: 6388931 (2002-05-01), Wilkins

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