Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2002-03-01
2003-09-09
Flynn, Nathan J. (Department: 2876)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S506000, C257S288000, C257S365000, C438S221000, C438S353000
Reexamination Certificate
active
06617663
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to semiconductor devices and methods for manufacturing the same. More particularly, the invention provides an improved pre-planarization processing method performed on a layer of a semiconductor device that has a large area of element forming regions which is subjected to a chemical-mechanical polishing (CMP) process.
With increased miniaturization and higher integration of semiconductor elements, there has been a reduction in the line-width of gate electrodes and wirings as well as a reduction in pitches. Accordingly, it is important to evaluate the lithography techniques used to form gate electrodes and wirings, and the film quality used to manufacture elements. These conditions are evaluated in advance using an evaluation wafer. A variety of patterns are formed in the evaluation wafer in order to evaluate various manufacturing steps. These patterns correspond to elements in an actual design, and include various conditions with measurements and pitches that correspond to those of the actual design. Evaluation wafers of this type are sometimes referred to as TEG (Test Element Group) wafers.
In recent years, the number of wiring layers has increased along with further device miniaturization and higher integration of semiconductor elements. Chemical-mechanical polishing (CMP) has become indispensable for planarizing formed layers. In the CMP process, concave and convex portions in a layer to be planarized are smoothed out after a predetermined time by selectively creating different polishing rates by applying different pressures to the concave and convex portions and selectivity for polishing surface by using slurry.
With the evaluation wafer technique described above, the CMP process is also used for planarizing layers of the semiconductor device. FIGS.
9
(
a
) and
9
(
b
) illustrate a case in which trench element isolating insulation films are formed as element isolation regions.
FIGS. 9
(
a
) and
9
(
b
) provide cross-sectional views of intermediate steps for forming trench element isolation regions according to a conventional technique. As shown in
FIG. 9
(
a
), a mask pattern of a nitride film (silicon nitride film or the like)
92
is formed on a silicon semiconductor substrate
91
, and element isolation trenches
93
are formed by etching. After the trenches
93
are oxidized (not shown), an oxide film
94
is formed by a chemical vapor deposition (CVD) method. The oxide film
94
is formed in different deposit levels according to the concave and convex portions of the trenches
93
.
An evaluation wafer
91
is provided with an element region
95
having a large area where gate wirings are laid at predetermined pitches. As a result, the oxide film
94
on the element region
95
having a large area is deposited higher than other regions, and forms a large platform area (convex section)
941
.
A polishing pad used in the CMP process applies pressure to the convex sections of the layer to be planarized (the oxide film
94
) that is greater than that applied to the concave sections. This creates greater polishing rates at the convex sections than in the concave sections. The pressure of the polishing pad at a large area convex portion having is widely dispersed, however, and the polishing rate at the convex region is thereby reduced. In other words, the platform region
941
on the element region
95
cannot be planarized in the same manner as the other fine concave and convex regions where the deposit level is lower, and errors in the planarization increase.
Accordingly, as shown in
FIG. 9
(
b
), the platform region
941
of the oxide film
94
on the element region
95
with an area larger than other regions is entirely etched to a certain level using a lithography technique to approximate its level to the deposit level in the other regions. A protruded section
942
is formed due to a forming margin provided in a resist mask pattern. When the CMP process is then performed after this structure has been formed, planarized levels with small errors are created. Although not shown, the nitride film
92
is detected as a stopper film for the CMP process, and then the nitride film is removed. As a result, a trench element isolating insulation film in which the oxide film
94
is embedded in the trenches
93
is formed.
However, problems of dishing characteristic to the CMP process may not be avoided in the countermeasure provided for the platform region
941
of the oxide film
94
with a large area, such as the one shown in FIG.
9
(
b
). Since the platform region
941
with a large area has no trench, and therefore almost no concave and convex portions, dishing is likely to occur.
FIG. 10
shows a cross-section obtained at the time of detection of the nitride film
92
as a stopper film for the CMP process after planarization is conducted on the structure shown in FIG.
9
(
b
). Dishing occurs over the large area element region
95
, such that the nitride film
92
is exposed earlier than other regions, and the CMP process is completed. If the process proceeds to the step of removing the nitride film
92
, the nitride film
92
cannot be completely removed because the oxide film
94
remains on the nitride film
92
.
In order to avoid the problem described above, the CMP process is unavoidably and excessively performed, even after the nitride film
92
has been detected, for a period of time expected to remove the oxide film
94
that remains on the nitride film
92
. As a consequence, problems occur in that the CMP process efficiency is decreased, deterioration of the polishing pad progresses, and the film thickness of the oxide film (
94
) as a trench element isolation film varies.
The present invention has been made in view of the circumstances described above. The invention provides a pre-planarization processing method that can readily reduce dishing even in a large area region with few concave and convex portions. By using the invention, a planarized level can be created with few variations in the film thickness and with a minimal amount of polishing.
SUMMARY OF THE INVENTION
The invention provides a method for semiconductor device manufacturing in which a platform region is formed, typically on a semiconductor substrate. A dummy pattern is then formed in the platform region. The dummy pattern includes a plurality of regions of differing heights. The dummy pattern is then subjected to chemical-mechanical polishing to remove at least a portion of the platform region. Provision of the dummy pattern provides polishing of enhanced uniformity in comparison with previously known methods.
In accordance with one embodiment of the present invention, a dummy pattern having a plurality of concave and convex portions with a specified depth is formed entirely in a platform region. As a result, the selectivity of polishing rates created by the chemical-mechanical polishing pad can be effectively used, and slurry uniformly spread throughout the concave portions so that uniform CMP processing is accomplished.
The dummy pattern may preferably be provided by forming a lattice pattern of grooves by a photolithography technique. Alternatively, the dummy pattern may be provided by forming a plurality of openings by a photolithography technique. Other features and advantages of the invention will be apparent from the following detailed description, taken in conjunction will the accompanying drawings which illustrate, by way of example, various features of embodiments of the invention.
REFERENCES:
patent: 5976949 (1999-11-01), Chen
patent: 6495855 (2002-12-01), Sawamura
Horie Tomokazu
Sugiyama Shin-ichi
Flynn Nathan J.
Hogan & Hartson LLP
Seiko Epson Corporation
Wilson Scott
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