Adjustable, full CMOS input buffer for TTL, CMOS, or low...

Details Adjustable, full CMOS input buffer for TTL, CMOS, or low... Adjustable, full CMOS input buffer for TTL, CMOS, or low...

2000-02-07

2002-01-01

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C326S031000, C326S081000, C326S083000

Reexamination Certificate

active

06335633

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuits and more particularly to input buffer circuits at an external interface of integrated circuits that will receive digital signals from external circuitry, buffer the digital signals, and convert the digital signals to voltages level acceptable to internal circuitry within the integrated circuits.
2. Description of Related Art
The design of input buffer circuits for integrated circuits is well known in the art as shown in U.S. Pat. No. 4,475,050 (Noufer), U.S. Pat. No. 5,304,867 (Morris) and U.S. Pat. No. 5,355,033 (Jang). The input buffer is used to accept an input signal that will comply to the electrical characteristics for logic technologies such as transistor-transistor logic (TTL), Low Voltage TTL (LVTTL), Stub Series Terminated Logic (SSTL), and Gunning Transceiver Logic (GTL). The electrical characteristics for these logic technologies are often different from the electrical characteristics of the internal circuitry of the integrated circuits.
The input buffer should be simple in design, have minimal time delay, consume low power, and be highly tolerant to external electrical noise. Additionally the operating characteristics of the input buffer should vary minimally to variations in semiconductor processing parameters, power supply voltage, and temperature.
The standard input buffers of Complementary Metal Oxide Semiconductor (CMOS) integrated circuits are usually either a simple CMOS inverter that may or may not incorporate hysteresis (a Schmitt trigger) as shown in
FIG. 1
or a differential amplifier as shown in
FIG. 2
The CMOS inverter as shown in
FIG. 1
will have a trip point or threshold where the voltage level of the input signal will cause the output to change from the voltage level of a first logic state (0) to the voltage level of a second logic state (1) or from the second logic state (1) to the first logic state (0). The trip point can be modified by the appropriate design of the transistors within the input buffer so that the trip point will correspond as nearly as possible to the midpoint of the possible voltage swing of the input signal.
The CMOS inverter circuit of
FIG. 1
is generally the faster approach because the input controls both the NMOS and PMOS transistors by forcing one to a non-conducting state while forcing the other to a conducting state. The effective circuit amplification of this technique is very large. The trip point of the CMOS inverter of
FIG. 1
is strongly dependent upon the power supply voltage source and the processing parameters. The variations of the power supply voltage source and the processing parameters will effectively vary the trip point of the CMOS inverter by nearly 0.8V. While this range is satisfactory for logic technologies such as LVTTL, it is not acceptable for such technologies as SSTL.
The differential amplifier input buffer of
FIG. 2
will compare the voltage level of the input signals to that of a reference voltage Vref. If the voltage of the input signals transits between a voltage greater than the reference voltage Vref and a voltage less than the reference voltage Vref, the output will transit between the first logic state (0) and the second logic state (1). Since the reference voltage Vref can be precisely designed to be insensitive to variations in semiconductor processing parameters, power supply voltage, and temperature, the trip point can be precisely controlled.
Referring now to
FIG. 1
for a more detailed description of a CMOS inverter incorporating a Schmitt trigger. The above described input signal is applied to the input terminal IN
ext
. The input terminal IN
ext
is generally the input pad of a semiconductor chip and is connected to the external circuitry that will be the source of the input signal. The N-channel metal oxide semiconductor (NMOS) transistors N
1
, and N
2
and the P-channel metal oxide semiconductor (PMOS) transistors P
2
and P
3
are configured for the CMOS inverter. The gates of the NMOS transistors N
1
and N
2
and the PMOS transistors P
2
and P
3
are connected to the input terminal IN
ext
. The PMOS transistor P
1
is used to activate and deactivate the CMOS inverter. An enable signal at the ENABLE terminal is connected to the gate of the PMOS transistor P
1
. If the enable signal is at the first logic state (0) it will cause the PMOS transistor P
1
to conduct and the NMOS transistor N
3
to cease conduction thus activating the CMOS inverter. However, if the enable signal is at the second logic state (1), it will cause the PMOS transistor P
1
to cease conduction and the NMOS transistor N
3
to conduct thus deactivating the CMOS inverter and bringing the output to the first logic state (0).
When the CMOS inverter is activated and the input signal begins to transit from a low voltage level or the first logic state (0) to a high voltage level or the second logic state (1), the NMOS transistors N
1
and N
2
begin to conduct and the PMOS transistors P
2
and P
3
begin to cease conduction. Once the input signal reaches the trip point, the NMOS transistors N
1
and N
2
are in equal conduction with the PMOS transistors P
2
and P
3
and the output is near mid-range. The input signal continues to the second logic state (1). As the loading capacitance attached to the output terminal OUT
int
is discharged through NMOS transistors N
1
and N
2
, the voltage level at the output terminal OUT
int
will approach the voltage level of the low supply voltage source. Conversely, when the input signal begins to transit from a high voltage level or the first logic state (1) to the low voltage level or the second logic state (0), NMOS transistors N
1
and N
2
begin to cease conduction and the PMOS transistors P
2
and P
3
begin to conduct. As the input signal traverses the trip point, the NMOS transistors N
1
and N
2
become equal in conduction with the PMOS transistors P
2
and P
3
. The input signal continues to the first logic state (0) The loading capacitance at the output terminal OUT
int
is now charged to the voltage level of the high supply voltage source through the PMOS transistors P
2
and P
3
.
The trip point can be modified to provide hysteresis or a variation in the level of the trip points for the input signal going from the first logic state (0) to the second logic state (1) versus that of the input signal going from the second logic state (1) to the first logic state (0). The hysteresis is established by either the NMOS transistors N
4
or the PMOS transistors P
4
, which may be optionally added to the circuit to adjust the hysteresis as needed
When the input signal at the input terminal IN
ext
is at the second logic state (1) and the output signal at the output terminal OUT
int
is at the first logic state (0), the PMOS transistor P
4
is in full conduction (the gate to source voltage of PMOS transistor P
4
V
gs
is equal to the negative high supply voltage). As the input signal IN
ext
traverses from the second logic state (1) to the first logic state (0), The NMOS transistors N
1
and N
2
begin to conduct so there is current in the drain to source path of the series chain of transistors P
1
, P
2
, P
3
, N
1
, and N
2
. Since the PMOS transistor P
4
is fully conducting, the common node to the PMOS transistors P
2
, P
3
, and P
4
is essentially connected to the low supply voltage source. This common node is the source of the PMOS transistor P
3
and consequently the PMOS transistor P
3
is held in a non-conducting state. As the input signal continues to fall toward the first logic state (0), the PMOS transistor P
2
begins to conduct harder and begins to raise the common node to the PMOS transistors P
2
, P
3
, and P
4
from the low supply voltage level toward the high supply voltage level. The ratio of the sizes of the PMOS transistors P
2
and P
4
is such that PMOS transistor P
3
is conducting when the input signal has reached the midrange of the signal swing (about ½ the high supply voltage level). As soon as the PMOS transistor P
3
is in full c

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