Adjustable delay circuit for setting the speed grade of a semico

Details Adjustable delay circuit for setting the speed grade of a semico Adjustable delay circuit for setting the speed grade of a semico

1997-08-22

1999-07-27

Mai, Son

Static information storage and retrieval

Read/write circuit

Signals

36518902, G11C 700

Patent

active

059301821

ABSTRACT:
An integrated circuit having an adjustable delay circuit such that the timing characteristics of the integrated circuit can be adjusted. A method for adjusting the timing characteristics of the integrated circuit in order to insure that the integrated circuit meets the specifications of a lower speed grade in the event that the integrated circuit fails the specifications of a targeted speed grade.

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patent: 5703815 (1997-12-01), Kuhara et al.
patent: 5748553 (1998-05-01), Kitamura

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