Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-02-11
2003-04-15
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230060, C365S202000, C365S194000
Reexamination Certificate
active
06549471
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to differential driver circuitry and in particular the present invention relates to differential driver circuitry with reduced power consumption.
BACKGROUND OF THE INVENTION
Differential driver circuitry traditionally includes two inverter circuits to provide complimentary output signals. The inverters consume power when driving the output signals. Increased power consumption is experienced when changing the outputs from one data state to another. Different power conservation techniques have been implemented to reduce the power used by the drivers. For example, power-down signals can be used to either reduce the drive level or disable unused buffers and drivers. In addition, unbalanced inverters can be used to steer current in specific directions, such as a clock driver circuit having unbalanced inverters to provide a stronger device pull-up on clock and a stronger pull-down device on clock compliment.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a differential driver circuit that has a reduced current consumption during operation.
SUMMARY OF THE INVENTION
The above-mentioned problems with differential driver circuitry and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, an integrated circuit differential driver comprises first and second driver circuits respectively coupled to first and second output connections, and equilibration circuitry coupled between the first and second output connections to selectively equalize voltages on the first and second output connections.
In another embodiment, a differential driver circuitry comprises a first driver circuit to provide an output signal on a first output connection in response to a first input signal, a second driver circuit to provide an output signal on a second output connection in response to a second input signal, and tri-state circuitry to selectively place the first and second driver circuits in tri-state. An equilibration circuit is coupled between the first and second output connections to selectively equalize voltages on the first and second output connections while the first and second driver circuits are tri-stateed.
A memory device comprises a memory array to store data, first and second output connections to provide differential output signals, and a differential driver circuit coupled to the two output connections. The differential driver circuit comprises first and second drivers respectively coupled to the first and second output connections, and equilibration circuitry coupled between the first and second output connections to selectively equalize voltages on the first and second output connections.
A method of operating a driver circuit comprises receiving differential input signals, placing the driver circuit in a tri-state in response to the input signals transitioning logic levels, and performing an equilibration operation on output connections of the driver circuit while the driver circuit is tri-state.
Another method of operating a driver circuit comprising receiving differential input signals, detecting a transition in the input signals, and placing the driver circuit in a tri-state for a predetermined period of time when the transition is detected. A transistor coupled between output connections is activated for the predetermined time period to perform an equilibration operation on output connections of the driver circuit.
REFERENCES:
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patent: 5875140 (1999-02-01), Merritt et al.
patent: 5933372 (1999-08-01), Seyyedy et al.
patent: 6330196 (2001-12-01), Protzman
patent: 6381180 (2002-04-01), Merritt et al.
patent: 6411553 (2002-06-01), Wright et al.
patent: 6452833 (2002-09-01), Akita et al.
Hoang Huan
Leffert Jay & Polglaze P.A.
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