Adiabatic CMOS design

Details Adiabatic CMOS design Adiabatic CMOS design

2011-03-08

2011-03-08

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C326S032000, C326S088000, C326S103000

Reexamination Certificate

active

07902861

ABSTRACT:
An integrated circuit comprising a plurality of CMOS modules (10) connected in series with each other, each module (10) being connected between first and second reference lines (Vdd, Vss). A first transistor (54) is provided between at least one of the modules (10) and the first reference line (Vdd) and a second transistor (52) is provided between one of the modules (10) and the second reference line (Vss) and capacitors (C25, C26) are provided in parallel with the transistors (52, 54) such that they are driven as current sources (I1, I2). As a result power dissipation and leakage current is reduced.

REFERENCES:
patent: 5097159 (1992-03-01), Seki et al.
patent: 5726946 (1998-03-01), Yamagata et al.
patent: 6097253 (2000-08-01), Hissen
patent: 2002/0036942 (2002-03-01), Ooishi
patent: 2006/0030110 (2006-02-01), Kumura et al.

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