Static information storage and retrieval – Read/write circuit – Simultaneous operations
Patent
1989-08-07
1993-06-29
Clawson, Jr., Joseph E.
Static information storage and retrieval
Read/write circuit
Simultaneous operations
36518905, 36523006, 36523008, 371 101, 371 102, 371 103, 307449, 307463, G11C 700
Patent
active
052240711
ABSTRACT:
An addressable memory unit has address input buffer circuits which output a pair of output connections on which, in read or write mode, two signals which are complementary to one another are present but which may also adopt equal values in such a manner as to cause a predecoder and line selector to select all or none of the selection lines controlling the cells of the memory accessed.
REFERENCES:
patent: 4412309 (1983-10-01), Kuo
patent: 4543647 (1985-09-01), Yoshida
patent: 4593383 (1986-06-01), Armstrong et al.
patent: 4651304 (1987-03-01), Takata
patent: 4849939 (1989-07-01), Muranaka et al.
patent: 4852066 (1989-07-01), Kai
patent: 4855621 (1989-08-01), Hoffman et al.
patent: 4879681 (1989-11-01), Miwa et al.
patent: 4879689 (1989-11-01), Atsumi et al.
R. J. Hengst et al, "Address Buffer", IBM Technical Disclosure Bulletin, vol. 26, No. 12, May 1984, pp. 6469-6470.
Davies Thomas J.
O'Connell Cormac
Ontrop Hans
Pfennings, deceased Leonardus C. M. G.
Phelan Cathal G.
Clawson Jr. Joseph E.
Slobod Jack D.
U.S. Philips Corp.
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