Address selecting circuitry for semiconductor memory device

Details Address selecting circuitry for semiconductor memory device Address selecting circuitry for semiconductor memory device

1977-08-15

1978-08-01

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365182, 307238, G11C 1140

Patent

active

041047338

ABSTRACT:
In an address selecting circuitry for a semiconductor memory device including a matrix of memory cells arrayed in rows and columns, an address input signal A.sub.i for any given bit of address data is applied to a single address signal setting circuit to produce a set of two different logic signals a.sub.i and a.sub.i in accordance with the state of the address input signal, and the set of logic signals a.sub.i and a.sub.i are supplied to a row decoder driving circuit as well as a column decoder driving circuit which are connected to row and column decoder circuits respectively. The row and column decoder driving circuits are driven by row and column decoder drive timing signals respectively to drive selected row and column decoders so that predetermined row and column lines are selected.

REFERENCES:
patent: 3969706 (1976-07-01), Proebsting

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