Static information storage and retrieval – Read/write circuit – Testing
Patent
1992-05-26
1994-07-19
Gossage, Glenn
Static information storage and retrieval
Read/write circuit
Testing
365193, 36523002, 365233, 371 211, 371 212, G11C 2900, G11C 11407
Patent
active
053315960
ABSTRACT:
An address multiplexed dynamic random access memory (RAM) which has both a normal operation mode and a test mode capability is provided. The test mode is initiated in response to particular signal level combinations of both the row address strobe (RAS) and column address strobe (CAS) signals and the write enable (WE) signal. Since the signal level combinations employed in connection with implementing the test mode are unused in the normal operating mode of the dynamic RAM, additional external terminals are unneeded. This dynamic RAM employs multiplexing circuitry on both the input side as well as on the output side of the dynamic RAM, which multiplexing circuitry is controlled during normal operation by select signals from a decoder and during the test mode by a test signal which allows accessing of data at all of the common complementary data lines by the testing circuitry so as to determine whether there is consistency or inconsistency of the data being read out for testing.
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"Mitsubishi-Giho" (vol. 59, No. 9, Mitsubishi Electric Corp. 1985, pp. 60-63).
Etoh Jun
Kimura Katsutaka
Miyazawa Kazuyuki
Shimohigashi Katsuhiro
Gossage Glenn
Hitachi , Ltd.
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