Address generating circuit for data compression

Details Address generating circuit for data compression Address generating circuit for data compression

1998-10-26

2000-12-26

Tadayon, Bijan

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

382232, 382233, G06F 1200

Patent

active

061674818

ABSTRACT:
It is an object of the invention to provide an address generating circuit for data compression capable of generating addresses in accordance with address compression blocks from any address in a failure analysis memory by executing an operation of the compression rate to an address compression block end by a CPU based on a start address position and an address compression rate. At an address generation starting time, a start address data b is held by a flip flop 3B and it is loaded at the same time into an up counter 5B as an output of a selector 4B, so that address generating operation is performed by a single clock. It is possible to generate addresses in accordance with the width of the address compression rate 2h in the address compression blocks for partitioning memory areas of an analysis memory by providing a selector 7B for selecting the address compression rate 2h when the address carry signal is outputted while data of an address compression rate 1g serves as a load data of a down counter 9B at the time of starting generation of addresses in case that an external address generating control circuit calculates the address compression rate 1g based on the start address data b and address compression rate 2h.

REFERENCES:
patent: 5226135 (1993-07-01), Mishina et al.
patent: 5485557 (1996-01-01), Sato et al.
patent: 5812146 (1998-09-01), Sato et al.
patent: 5861892 (1999-01-01), Sato et al.

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