Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Patent
1996-10-18
2000-06-13
Ngo, Chuong Dinh
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
708710, 708714, G06F 750
Patent
active
060760982
ABSTRACT:
A circuit is disclosed herein which generates the sum of two numbers (A and B) and the sum plus 1 in parallel so as not to take any additional time to generate the sum plus 1 value. The circuit comprises a carry look-ahead (CLA) tree portion and a summer portion. The CLA tree portion generates carry bits, as well as the logical relationship A.sub.i XOR B.sub.i, for application to a summer for bit position i. The carry bits contain information for either inverting or not inverting the A.sub.i XOR B.sub.i bit for both the sum and the sum plus 1 output of the summer. The sum bit and sum plus 1 bit are generated at approximately the same time.
REFERENCES:
patent: 3700875 (1972-10-01), Saenger et al.
patent: 4464729 (1984-08-01), Mlynek
patent: 5278783 (1994-01-01), Edmondson
patent: 5283755 (1994-02-01), Bechade
patent: 5615140 (1997-03-01), Ishikawa
patent: 5631860 (1997-05-01), Morinaka
Arpad Barna and Dan I Porat, "Arithmetic Circuits," Integrated Circuits in Digital Electronics, A Wiley-Interscience Publication, John Wiley & Sons, pp. 236-248. 1973.
Ngo Chuong Dinh
Samsung Electronics Co,. Ltd.
LandOfFree
Adder for generating sum and sum plus one in parallel does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Adder for generating sum and sum plus one in parallel, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Adder for generating sum and sum plus one in parallel will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2078423