Adaptive reader-writer lock

Details Adaptive reader-writer lock Adaptive reader-writer lock

2008-05-06

2010-06-29

Rinehart, Mark (Department: 2111)

Electrical computers and digital data processing systems: input/

Access locking

C718S104000

Reexamination Certificate

active

07747805

ABSTRACT:
A method and computer system for dynamically selecting an optimal synchronization mechanism for a data structure in a multiprocessor environment. The method determines a quantity of read-side and write-side acquisitions, and evaluates the data to determine an optimal mode for efficiently operating the computer system while maintaining reduced overhead. The method incorporates data received from the individual units within a central processing system, the quantity of write-side acquisitions in the system, and data which has been subject to secondary measures, such as formatives of digital filters. The data subject to secondary measures includes, but is not limited to, a quantity of read-side acquisitions, a quantity of write-side acquisitions, and a quantity of read-hold durations. Based upon the individual unit data and the system-wide data, including the secondary measures, the operating system may select the most efficient synchronization mechanism from among the mechanisms available. Accordingly, efficiency of a computer system may be enhanced with the ability to selectively choose an optimal synchronization mechanism based upon selected and calculated parameters.

REFERENCES:
patent: 5287521 (1994-02-01), Nitta et al.
patent: 5442758 (1995-08-01), Slingwine et al.
patent: 5596754 (1997-01-01), Lomet
patent: 5608893 (1997-03-01), Slingwine et al.
patent: 5615373 (1997-03-01), Ho
patent: 5727209 (1998-03-01), Slingwine et al.
patent: 5729765 (1998-03-01), Cheng
patent: 5737611 (1998-04-01), Vicik
patent: 5761659 (1998-06-01), Bertoni
patent: 5838912 (1998-11-01), Poon et al.
patent: 5872981 (1999-02-01), Waddington et al.
patent: 5960194 (1999-09-01), Choy et al.
patent: 5983225 (1999-11-01), Anfindsen
patent: 6405274 (2002-06-01), Chan
patent: 6546443 (2003-04-01), Kakivaya et al.
patent: 6678772 (2004-01-01), McKenney
patent: 7191272 (2007-03-01), McKenney
McKenney, P., Proceeding of IASTED International Conference Parallel and Distributed Computing and System, “Practical Performance Estimation On Shared-Memory Multiprocessors,” Nov. 3-6, 1999.
Lim et al., “Reactive Synchronization Algorithms For Multiprocessors”, Jun. 1995.

Affiliated with

Also associated with

Rating

Adaptive reader-writer lock does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Adaptive reader-writer lock, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Adaptive reader-writer lock will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4211295