Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-07-16
2004-10-19
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06807655
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to techniques for screening of integrated circuit dies during semiconductor manufacturing. More particularly, the present invention relates to statistical methodologies used in screening manufactured integrated circuit dies.
2. Description of the Related Art
Semiconductor wafer fabrication involves a series of processes used to create semiconductor devices and integrated circuits (IC's) in and on a semiconductor wafer surface. Fabrication typically involves the basic operations of layering and patterning, together with others such as doping, and heat treatments. Layering is an operation used to add thin layers of material (typically insulator, semi-conductor or conductor) to the surface of the semiconductor wafer. Patterning is an operation that is used to remove specific portions of the top layer or layers on the wafer surface. Patterning is usually accomplished through the use of photolithography (also known as photomasking) to transfer the semiconductor design to the wafer surface.
Typically, a large number of dies are formed on a wafer using these methods.
Many of these dies may have defects occurring during the fabrication process, for example during the patterning of layers, which affect the reliability of the die. Some defects, for example, directly affect the functionality of the circuit resulting in functional failure. Other defects may adversely affect the reliability of the circuit resulting in an early lifetime failure or failure under varying operating conditions.
Normal process variations may produce natural variations in device electrical characteristics. For example, current measured in a CMOS transistor may vary in accordance with the channel length. The target channel length is specified by design to meet performance characteristics like current consumption and device speed. However, as illustrated in
FIG. 1A
, process variations resulting in a larger channel length (L-effective) will result in a device having low speed and low current, though for all other purposes the device is normal. Conversely, process variations may result in an effective channel length smaller than the target length, thus resulting in a high speed, high current device.
Normal process variations will produce an intrinsic probability distribution for a measured parameter. A data point is an “outlier” if it comes from a different probability distribution or from a different deterministic model than the remainder of the data. It is important to effectively screen the dies to identify and separate outliers from the intrinsic distribution.
One conventional test measures the quiescent current (IDDQ) to differentiate between good and defective die. The IDDQ testing relies on detecting the defective chip by monitoring the quiescent current. Identification of defects is based on the fact that a CMOS circuit does not draw any significant current when in a stable situation. Thus, in a quiescent state, only the leakage current flows, which is often negligible. A defect such as a short between transistors may cause the quiescent current to increase, indicating a manufacturing defect. Such defects may cause either functional failures or early lifetime failures.
IDDQ testing is a sensitive technique, able to detect such problems in an early stage and offers an alternative to expensive or time-consuming approaches such as burn-in testing. But the downsizing of semiconductor devices to the sub-micron level has made it increasingly difficult to identify and separate outliers from the intrinsic die distribution using conventional quiescent current testing and evaluation. As the devices have become smaller, the gap between leakage current under normal conditions and quiescent current caused by manufacturing defects has narrowed. As a result, tradeoffs are often made between yield and reliability levels. That is, the difficulty in differentiating between normal and defective dies has required a sacrifice in the yield to achieve certain reliability levels or conversely lower reliability guarantees to achieve certain yield levels.
Accordingly, it is desirable to provide a more effective electrical screening and evaluation method for die without compromising yield factors.
SUMMARY OF THE INVENTION
The present invention provides an off tester adaptive screening method for determining defective die and controlling reliability vs. yield trade-offs. The present invention utilizes the data for a die lot to adaptively set parametric limits for segregating good die from defective die. The off tester data processing method for die screening and disposition uses limits that are adaptive to the distribution at hand, within certain bounds, and can be adjusted form a single point of intervention depending on the quality requirements.
In one aspect, a method of determining the disposition of a semiconductor die includes measuring at least a first and a second parameter for each of a plurality of dies. The plurality of dies are quantized into a plurality of brackets according to the values of the first measured parameter. For each of the plurality of brackets, a statistical relationship is determined for the values of the second parameter for each of the dies in the bracket. The statistical relationship is used to determine an intrinsic distribution function for all of the dies. An adaptive screening limit is set corresponding to the intrinsic distribution function. Dies falling outside the adaptive screening limit are identified as defective or unreliable. In another aspect, the first and second parameters are selected from the group consisting of quiescent current and speed for the dies. In yet another aspect, the group consists of channel length, current, and speed for the dies. In yet another aspect, the group consists of oxide thickness, current, and speed for the dies.
These and other features and advantages of the present invention are described below with reference to the drawings.
REFERENCES:
patent: 5787190 (1998-07-01), Peng et al.
patent: 6167545 (2000-12-01), Statovici et al.
patent: 6496418 (2002-12-01), Kawahara et al.
patent: 6524873 (2003-02-01), Satya et al.
Abercrombie David
Cota Kevin
Madge Robert
Rehani Manu
Beyer Weaver & Thomas
Dinh Paul
LSI Logic Corporation
Siek Vuthe
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