Adaptive current sense amplifier with direct array access...

Static information storage and retrieval – Read/write circuit – Differential sensing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S207000, C365S205000, C327S051000, C327S052000

Reexamination Certificate

active

07821859

ABSTRACT:
A current sense amplifier can include an active load circuit having a first load device and second load device coupled in parallel to a first power supply node. A first load device and second load device can provide an impedance that varies according to a potential at a load control node. A reference current circuit can be coupled between the first load device and a second power supply node that includes a current reference section that provides an impedance according to a bias voltage. A data current circuit can be coupled between the second load device and a plurality of memory cells. An adaptive bias circuit can be coupled between the first power supply and the second power supply node and can include a bias section coupled to the load control node that provides an impedance according to the bias voltage.

REFERENCES:
patent: 3636530 (1972-01-01), Mark et al.
patent: 3676717 (1972-07-01), Lockwood
patent: 3950737 (1976-04-01), Uchida et al.
patent: 4044343 (1977-08-01), Uchida
patent: 4128773 (1978-12-01), Troutman et al.
patent: 4132904 (1979-01-01), Harari
patent: 4271487 (1981-06-01), Craycraft et al.
patent: 4342101 (1982-07-01), Edwards et al.
patent: 4800533 (1989-01-01), Arakawa
patent: 4878203 (1989-10-01), Arakawa
patent: 5029132 (1991-07-01), Arakawa
patent: 5065362 (1991-11-01), Herdt et al.
patent: 5097449 (1992-03-01), Cuevas
patent: 5168334 (1992-12-01), Mitchell et al.
patent: 5189641 (1993-02-01), Arakawa
patent: 5315177 (1994-05-01), Zagar et al.
patent: 5353248 (1994-10-01), Gupta
patent: 5426605 (1995-06-01), Van Berkel et al.
patent: 5436480 (1995-07-01), Yu
patent: 5440508 (1995-08-01), Pathak et al.
patent: 5488579 (1996-01-01), Sharma et al.
patent: 5496756 (1996-03-01), Sharma et al.
patent: 5602776 (1997-02-01), Herdt et al.
patent: 5732032 (1998-03-01), Park et al.
patent: 5734617 (1998-03-01), Zheng
patent: 5812477 (1998-09-01), Casper et al.
patent: 5864499 (1999-01-01), Rohparvar et al.
patent: 5875144 (1999-02-01), Zheng
patent: 5892712 (1999-04-01), Hirose et al.
patent: 5956269 (1999-09-01), Ouyang et al.
patent: 5978298 (1999-11-01), Zheng
patent: 5986932 (1999-11-01), Ratnakumar et al.
patent: 5999447 (1999-12-01), Naura et al.
patent: 6011742 (2000-01-01), Zheng
patent: 6016264 (2000-01-01), Lin
patent: 6084814 (2000-07-01), Casper et al.
patent: 6097618 (2000-08-01), Jenne
patent: 6122191 (2000-09-01), Hirose et al.
patent: 6125069 (2000-09-01), Aoki
patent: 6141247 (2000-10-01), Roohparvar et al.
patent: 6172907 (2001-01-01), Jenne
patent: 6181627 (2001-01-01), Casper et al.
patent: 6194738 (2001-02-01), Debenham et al.
patent: 6246623 (2001-06-01), Ingalls
patent: 6285586 (2001-09-01), Lung et al.
patent: 6297103 (2001-10-01), Ahn et al.
patent: 6363011 (2002-03-01), Hirose et al.
patent: 6373771 (2002-04-01), Fifield et al.
patent: 6384664 (2002-05-01), Hellums et al.
patent: 6420925 (2002-07-01), Fifield et al.
patent: 6469930 (2002-10-01), Murray
patent: 6490203 (2002-12-01), Tang
patent: 6532169 (2003-03-01), Mann et al.
patent: 6553556 (2003-04-01), Blodgett
patent: 6556487 (2003-04-01), Ratnakumar et al.
patent: 6574145 (2003-06-01), Kleveland et al.
patent: 6608498 (2003-08-01), Khoury
patent: 6617914 (2003-09-01), Kothandaraman
patent: 6621324 (2003-09-01), Fifield et al.
patent: 6625080 (2003-09-01), Casper et al.
patent: 6633506 (2003-10-01), Casper et al.
patent: 6674665 (2004-01-01), Mann et al.
patent: 6714469 (2004-03-01), Rickes et al.
patent: 6741117 (2004-05-01), Lee
patent: 6759895 (2004-07-01), Takami
patent: 6781916 (2004-08-01), McClure
patent: 6983404 (2006-01-01), Cutter et al.
patent: 7031189 (2006-04-01), Pascucci
patent: 7146585 (2006-12-01), Blodgett
patent: 7149114 (2006-12-01), Taheri et al.
patent: 7339848 (2008-03-01), Stansell et al.
patent: 7342424 (2008-03-01), Kang et al.
patent: 7342836 (2008-03-01), Taheri et al.
patent: 7426142 (2008-09-01), Stansell et al.
patent: 2002/0057597 (2002-05-01), Fuchigami et al.
patent: 2005/0213387 (2005-09-01), Kubo et al.
U.S. Appl. No. 11/415,694, filed May 1, 2006, Stansell et al.
U.S. Appl. No. 11/726,525, filed Mar. 21, 2007, Stansell, Galen.
USPTO Miscellaneous Action for U.S. Appl. No. 11/343,341 dated Jan. 18, 2008; 2 pages.
USPTO Notice of Alllowance for U.S. Appl. No. 11/343,341 dated Sep. 10, 2007, 7 pages.
U.S. Appl. No. 11/343,341: “Anti-Fuse Latch Circuit and Method Including Self-Test,” Stansell et al.; 51 pages.
USPTO Requirement for Restriction/Election for U.S. Appl. No. 11/701,650 dated Nov. 22, 2008; 6 pages.
U.S. Appl. No. 11/701,650: “Method for Validating the Programming Status of Nonvolatile Memory Elements,” Stansell; 44 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/415,694 dated May 6, 2008; 4 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/415,694 dated Nov. 1, 2007; 9 pages.
U.S. Appl. No. 11/415,694: “Device and Method for Sensing Programming Status of Non-Volatile Memory Elements,” Stansell et al.; 37 pages.
U.S. Appl. No. 09/892,164: “SONOS Latch and Application,” Mann et al.; 26 pages, filed on Jun. 26, 2001.
U.S. Appl. No. 10/368,528: “SONOS Latch and Application,” Mann et al.; 28 pages, filed on Feb. 18, 2003.
U.S. Appl. No. 11/726,525: “Anti-Fuse Latch Self-Test Circuit and Method,” Stansel et al., filed on Mar. 21, 2007; 29 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/726,525 dated Apr. 21, 2009; 7 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/726,525 dated Oct. 17, 2008: 5 pages.
USPTO Miscellaneous Action for U.S. Appl. No. 10/803,011 dated Mar. 18, 2005; 1 page.
USPTO Non-Final Rejection for U.S. Appl. No. 10/803,011 dated Dec. 9, 2005; 13 pages.
USPTO Final Rejection for U.S. Appl. No. 10/803,011 dated May 30, 2006; 13 pages.
U.S. Appl. No. 10/803,011: “Latched Circuit and Method for Writing and Reading Volthe and Non-Volatile Data to and from the Latch,” Taheri et al., filed on Mar. 17, 2004; 31 pages.
USPTO Notice of Allowance for U.S. Appl. No. 10/803,011 dated Aug. 3, 2006; 7 pages.
USPTO Miscellaneous Action for U.S. Appl. No. 11/234,429 dated Feb. 14, 2006; 2 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/234,429 dated Jun. 18, 2007; 7 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/234,429 dated Oct. 18, 2007: 5 pages.
U.S. Appl. No. 11/234,429: “One Time Programmable Latch and Method,” Taheri et al., filed on Sep. 23, 2005: 48 pages.
International Search Report of the International Searching Authority for International Application No. PCT/US2005/008154 mailed Jul. 1, 2005; 2 pages.
Written Opinion of the International Searching Authority for International Application No. PCT/US2005/008154 received Jun. 29, 2005; 5 pages.
USPTO Notice of Allowance for U.S. Appl. No. 09/703,151 dated Jun. 4, 2002; 5 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 09/703,151 dated Jan. 16, 2002; 5 pages.
USPTO Notice of Allowance for U.S. Appl. No. 07/361,033 dated Apr. 30, 1991; 3 pages.
USPTO Final Refection for U.S. Appl. No. 07/361,033 dated Jan. 18, 1991; 5 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 07/361,033 dated Jun. 12, 1990; 11 pages.
USPTO Notice of Allowance for U.S. Appl. No. 08/549,483 dated Jun. 8, 1996; 3 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 08/549,483 dated May 29, 1996; 5 pages.
USPTO Notice of Allowance for U.S. Appl. No. 08/846,558 dated Jul. 20, 1998; 3 pages.
USPTO Requirement Restriction for U.S. Appl. No. 09/136,694 dated Aug. 17, 1999; 4 pages.
Frohman-Bentchkowsky, “The Methal-Nitrice-Oxide-Silicon (MNOS) Transistor—Characteristics and Applications,” Proceedings of the IEEE, vol. 58, No. 8, Aug. 1970, pp. 1207-1219; 13 pages.
Donaldson et al., “SNOS 1K X 8 Static Nonvolatile RAM,” IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, Oct. 1982, pp. 847-851; 5 pages.
Hirose et al., “Non-Volatile Latch for FPGA Devices,” NVX Corporation, Jan. 10, 1995; 6 pages.
Hirose et al., “Non-Volatile Latch Description,” NVX Corporation, Nov. 1, 1995; 23 pages.
Hirose et al.,

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Adaptive current sense amplifier with direct array access... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Adaptive current sense amplifier with direct array access..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Adaptive current sense amplifier with direct array access... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4210917

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.