Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-07-26
2004-03-23
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000, C365S230010, C365S185090
Reexamination Certificate
active
06711076
ABSTRACT:
BACKGROUND OF THE INVENTION
FIG. 1A
shows a conventional static random access memory (“SRAM”) cell
50
, which is represented on a transistor level at
50
A and on a more general gate level at
50
B. On the transistor level, cell
50
includes PFET transistors M
1
and M
2
and NFET transistors M
3
through M
6
. Transistors M
1
and M
3
are configured as a conventional inverter, which is shown as U
2
in FIG.
1
A. Likewise, transistors M
2
and M
4
are configured as a conventional static inverter, which is shown as U
1
in FIG.
1
A. Inverter M
1
/M
3
(U
2
) is cross-coupled with inverter M
2
/M
4
(U
1
) to form the memory storage portion of cell
50
. The input of inverter M
2
/M
4
(U
1
), which is connected to the output of inverter M
1
/M
3
(U
2
) provides a true data storage node (A), and the input of inverter M
1
/M
3
(U
2
), which is connected to the output of inverter M
2
/M
4
(U
1
), provides a compliment data storage node (B). Transistors M
5
and M
6
function as switches to control access to the cell internal nodes A and B from the differential bitline, comprised of the true bitline BLT and the compliment bitline BLC. Their gates are connected to a Word Line (“LWL”) signal that when active (high) enables writing to and reading from the SRAM memory cell nodes A and B. The structure formed by inverters U
1
and U
2
is known as a cross-coupled inverter, or a latch, and is naturally a bistable element capable of storing either a ‘1’ or a ‘0’. The cell will always resolve nodes A and B to either a ‘1’ or ‘0’ and maintain this state unless the cell contains a defective device or connection. Detecting such defects during the SRAM test flow is often difficult and time consuming, and is the focus for this invention. The following description on how the SRAM cell functions will provide further background for the invention.
FIG. 2
shows a block diagram for an SRAM subarray. The subarray is a relatively small SRAM block containing all the necessary memory components needed to control the SRAM memory element or cell. A large SRAM chip will be comprised of many subarrays, each controlled and activated by a unique address. The subarray consists of an array of SRAM cells (
10
) arranged in rows and columns; local wordline drivers to control the row activation (
11
); subarray control circuitry (
12
) to synchronize and select the SRAM read and write operations; and column data path circuits comprised of the bitline restore devices (
13
), bitswitch multiplexors (
14
), and the data sense amplifier and write drivers (
15
). The column circuitry (
16
) and the local wordline drivers (
11
) are known as pitch circuits because they must physically reside on pitch with the SRAM cell. The small dimensions of the SRAM cell make it desirable to keep these pitch circuits as small and simple as possible to prevent an unnecessary increase to the memories size.
FIG.
3
. expands into the subarray to show the circuits in more detail. For simplicity, only one SRAM cell is shown, along with the necessary column circuits. Functional blocks are used to describe the subarray controls (blocks
20
,
21
,
22
,
23
, and
25
) and local wordline drivers (
24
). Prior to selecting the subarray to perform either an SRAM read or write cycle, the control inputs to the subarray are precharged low. These signals consist of a subarray select signal (
30
), the global wordline GWL (
31
), a column address COLADDR (
32
), and write control WRT (
33
). In the unselected state, the subarray will have internal subarray signal COLSEL (
35
) low. This results in all array control signals being placed in the unselected or precharged state. The local wordline LWL (
36
) will be low turning off the cell access transistors M
5
and M
6
and isolating them from the bitlines BLT/BLC; column multiplexor bitswitch signals RBSW (
37
) and WBSW (
38
) are high and low, respectively, isolating the columns bitline from the sense amplifier data lines DLT/DLC; and both the bitline precharge BLR (
39
) and the data line precharge SAMPRES (
40
) are active low, precharging the bitlines BLT/BLC and data lines DLT/DLC high. The bitline precharge PFETS consist of devices M
7
, M
8
, and M
9
, while the data line precharge devices consist of PFETS M
14
, M
15
, and M
16
. With the subarray signals all in the precharge state, the SRAM access is ready to begin.
The SRAM read begins when the subarray select
30
drives active high. SRAM address signals will select one global wordline GWL (
31
) to activate, and one of the column address signals COLADDR (
32
). The write control signal WRT (
33
) will remain low during the SRAM read cycle. The internal subarray signal COLSEL(
35
) will now drive high to start preparing the SRAMs controlling signals for the read operation. COLSEL (
35
) acts as a local synchronizing clock to precisely time the critical SRAM control signals. In this manner the bitline precharge BLR (
39
) and data line precharge SAMPRES (
40
) drive high to turn off precharge devices M
7
, M
8
, M
9
, M
14
, M
15
, and M
16
at the same time the local wordline LWL (
36
) selects high and the read bitswitch signal RBSW (
37
) drives low to electrically connect the array bitlines BLT/BLC to the sense amplifiers data lines DLT/DLC through devices M
10
and M
13
. With the bitline and data line precharge devices off, and cell devices M
5
and M
6
turned on when the local wordline LWL (
36
) drives high, the cell can now take control. If the cell contains a logical ‘1’ with node A low and B high, the bitline BLT will start to discharge through devices M
5
and M
3
(NFET of inverter U
2
, see FIG.
1
A), while BLC remains high near the power supply rail Vdd. With bitswitch PFETs M
10
and M
13
opened the data line signals DLT/DLC will follow the bitlines and node DLT will start to discharge. For reference FIG.
6
C. shows a simulation of the SRAM control signals on the top plot and the bitlines BLT/BLC and data lines DLT/DLC on the lower plot. Because the SRAM cell devices are very small and the bitline capacitance is relatively high, owing to the fact that many cells are connected onto and share a bitline, bitline BLT will discharge to ground very slowly. An amplifier circuit (comprised here of devices M
16
, M
17
, M
18
, M
19
and M
20
) is used to increase the performance of the SRAM read by amplifying a small difference between data line signals DLT/DLC to full CMOS levels (Vdd and GND). This prevents the cell from having to fully drive the bitlines and data lines to ground, significantly improving the cells read performance. The differential voltage between DLT and DLC is referred to as the signal margin. It is critical to allow enough differential to develop for a reliable amplification, but not so much differential that performance suffers. A timing system is used to precisely control the sense amplifier circuit. In this case a mimic, or dummy wordline DWL (
41
) is used to provide tracking with the array wordline. Signal DWL will control the sense amplifier control circuit (
21
) to time and activate the sense amplifier set signal SET (
42
). SET driving active high will turn on sense amplifier device M
20
and allow the small differential voltage on data lines DLT/DLC to resolve to full CMOS levels. DLT will drive to ground, and DLC will remain high. To increase the performance of the amplification, the highly capacitive bitline signals are isolated from the data lines DLT/DLC at the same time the sense amplifier is activated. Read bitswitch signal RBSW goes high to turn off bitswitch PFETS M
10
and M
13
. With the bitlines BLT/BLC no longer needed for signal development they are now be precharged for the next cycle by activating the bitline restore signal BLR (
39
) and turning on PFET devices M
7
, M
8
, and M
9
. The data line precharge will take place after signal SET (
42
) has been active long enough to transfer the amplified signal to the SRAMs global data bus (not shown) and subsequently to the next logic stage.
The SRAM write begins when the subarray select
30
drives active high. SRAM address s
Walsh Robert A.
Yoha Connie C.
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