Activ shunt-peaked logic gates

Details Activ shunt-peaked logic gates Activ shunt-peaked logic gates

2002-08-06

2004-09-07

Le, Don (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C326S083000, C326S121000

Reexamination Certificate

active

06788103

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed toward the field of logic gates, and more particularly toward high-speed logic gates.
2. Art Background
Data communication systems transport data at a speed defined by a predetermined data rate. The speed of transmitting data in modem broadband communication systems has rapidly increased in recent years. Today, data rates as high as 40 giga bits per second (“Gbps”) are required for the OC-768 optical networking standard.
These data communication systems include basic digital circuits, such as multiplexors, demultiplexors, and constituent logic gates. Thus, to operate at high data rates, the digital circuits must also switch at high speeds (i.e., the digital circuits require a high bandwidth of operation). In addition to operating at high speeds, the digital circuits must be designed to minimize power dissipation. Excessive power dissipation degrades integrated circuit performance by producing excessive heat.
Typically, high-speed logic circuits are designed based on bipolar emitter-coupled logic (“ECL”) or metal oxide semiconductor (“MOS”) current-mode logic (“CML”). These logic families operate using differential inputs, clocks and outputs.
FIG. 1
illustrates the conventional implementation of a current mode logic latch.
The digital logic circuits must be able to regenerate signals, so that multiple stages of digital circuits may be cascaded. As shown in
FIG. 1
, the CML latch circuit includes gain resistors RL
1
and RL
2
. To this end, gain resistors are used on digital logic circuits (e.g., ECL and CML) to maintain a direct current (“DC”) voltage swing on the drain of transistors
103
,
104
,
105
, and
106
.
One objective in designing high-speed logic circuits is to reduce the resistive-capacitive (“RC”) time constant at the output of the logic gate. The RC time constant is a product of the resistance, provided by the gain resistors, and the total capacitance at the output of the logic gate. A large RC time constant results in relatively slow rise times of the output signal voltage. In turn, the slow rise time limits the operating speed of the circuit. Thus, the time constant at the output of the logic gate dictates how fast the logic circuit may operate.
One technique for reducing the time constant in the output of the digital circuits is to reduce the gain resistors (e.g., R
L1
and R
L2
for the latch of FIG.
1
). However, if smaller gain resistors are used, the current flowing in the device must be increased in order to maintain the requisite voltage swing at the output of the gate. Thus, in order to attain the necessary increase in current, an increase in the device size is required. These larger device sizes, in turn, increase the load capacitance (input capacitance of a subsequent gate as well as drain capacitance internal to the gate), and therefore there is no enhanced speed performance of the gate.
Accordingly, it is desirable to provide digital logic circuits that maintain adequate output drive while switching at very high data rates. It is also desirable to provide digital logic circuits with increased performance that minimize power dissipation and device size.
SUMMARY OF THE INVENTION
A logic circuit employs a shunt peaked technique to enhance the switching speed of the circuit without an increase in power dissipation. A logic gate implements a digital circuit function. For example, the logic gate may comprise a latch or a multiplexor. In one embodiment, the logic circuit is a differential logic circuit. For this embodiment, the logic gate comprises differential inputs lines, a differential clock, and differential output lines. The shunt peaked logic circuit includes two resistive and two inductive elements. Specifically, for each differential output line, a resistive element is coupled in series to an inductive element so as to couple the circuit power supply voltage to the differential output line. Under this configuration, the bandwidth of the logic circuit is increased without an increase in power consumption.
The logic circuit may be implemented using CML or ECL logic. In one embodiment, for the CML implementation, the inductor elements comprise MOS transistors. The gates of the MOS transistors are coupled to one of the resistive elements, and the drains of the MOS transistors are coupled to a power supply voltage. The sources of the MOS transistors are coupled to the differential output lines. In addition, the resistive elements are coupled to a biasing voltage. In another embodiment, for the ECL implementation, the inductor elements comprise bipolar transistors. The bases of the bipolar transistors are coupled to the resistive elements, and the collectors of the bipolar transistors are coupled to a power supply voltage. The emitters of the bipolar transistors are coupled to the differential output lines. Each of the resistive elements is also coupled to a biasing voltage.


REFERENCES:
patent: 5043602 (1991-08-01), Flannagan
patent: 6366140 (2002-04-01), Warwar
M.M. Green, et al., OC-192 Transmitter in Standard 0.18&mgr;m CMOS, 2002.
J. Choma, Jr., “Actively Peaked Broadbanded Monolithic Amplifier,” Proceedings of the IEE, vol. 127, Part G, Apr. 1980, pp. 61-66.
E. Säckinger and W. Fischer, “A 3 GHz CMOS Limiting Amplifier for SONET OC-48 Receivers”, IEEE Journal of Solid-State Circuits, vol. 35, No. 12, Dec. 2000, pp. 1884-1888.
T. Lee, The Design of CMOS Radio Frequency Circuits, Cambridge University Press, High Frequency Amplifier Design, 1998, pp. 178-184.

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