ACS unit and method thereof

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Details

C714S794000, C714S804000

Reexamination Certificate

active

07861147

ABSTRACT:
An add-compare-select (ACS) unit generates first path metrics having a first bit-pair and a most significant bit-pair (MSB) each including a high bit and a low bit. A first ACS circuit produces the first bit-pair and a first carry. A limiting circuit generates the MSB based on the first carry, and limits the MSB to a first predetermined value. A MSB maximum select (MS) unit receives an MSB of second path metrics from another ACS unit, and compares the MSBs of the first and the second path metrics to determine MSB decision signals based on maximum likelihood selection. A MSB storage unit stores the MSB of the first path metrics. A reset unit resets the high bit of the MSB of the first path metrics to a second predetermined value when the high bits of the MSBs of the first and the second path metrics reach the first predetermined value.

REFERENCES:
patent: 6327316 (2001-12-01), Ikeda
patent: 7073118 (2006-07-01), Greenberg et al.
patent: 7117426 (2006-10-01), Wu et al.
patent: 7496159 (2009-02-01), Wu et al.
patent: 7506239 (2009-03-01), Sudhakar et al.
patent: 2005/0120287 (2005-06-01), Wu et al.
patent: 2006/0029145 (2006-02-01), Rajagopal et al.
patent: 2006/0143554 (2006-06-01), Sudhakar et al.

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