ACS circuit and Viterbi decoder with the circuit

Details ACS circuit and Viterbi decoder with the circuit ACS circuit and Viterbi decoder with the circuit

2006-09-27

2009-08-25

Baker, Stephen M (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07581160

ABSTRACT:
An ACS circuit and a Viterbi decoder with the circuit. The Add-Compare-Select (ACS) circuit comprises: two registers for storing two previous candidate state metrics; a first adder for adding the value stored in the first register and a first branch metric to generate a first addition result; a second adder for adding the value stored in the second register and the first branch metric to generate a second addition result; a comparator for comparing the values stored in the first register and the second register to generate a decision bit; and a multiplexer for selecting either the first addition result or the second addition result as a new output candidate state metric according to the decision bit. Due to the parallel processing of the adders and the comparator, the processing speed of a Viterbi decoder with the ACS will be increased.

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