Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-01
2010-10-19
Levin, Naum B (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C324S765010, C438S014000, C257S048000
Reexamination Certificate
active
07818698
ABSTRACT:
A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.
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Chang Gwan Sin
Chen Chien-Wen
Ho Chia-Ming
Su Ke-Ying
Levin Naum B
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
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