Access circuit with various access data units

Details Access circuit with various access data units Access circuit with various access data units

2006-09-19

2006-09-19

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C713S501000, C711S201000, C711S211000

Reexamination Certificate

active

07111122

ABSTRACT:
An access circuit for efficiently accessing a buffer memory in accordance with an instruction from an external circuit. An access data unit for accessing a SDRAM in one operation clock cycle of the access circuit may be switched between one byte, one word, and two words. The switching of the access data unit is performed in accordance with a data unit designation signal generated by decoding address data, which is provided to a control unit, with an address decoder. The memory interface receives a request signal that is in accordance with the data unit designation signal from a request generator and accesses the buffer memory in the access data unit that is in accordance with the request signal.

REFERENCES:
patent: 4766538 (1988-08-01), Miyoshi
patent: 5113369 (1992-05-01), Kinoshita
patent: 5745791 (1998-04-01), Peek et al.
patent: 6466581 (2002-10-01), Yee et al.
patent: 6486704 (2002-11-01), Hearn
patent: 6489805 (2002-12-01), Au et al.
patent: 2003/0161351 (2003-08-01), Beverly et al.

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