Acceleration of etch selectivity for self-aligned contact

Details Acceleration of etch selectivity for self-aligned contact Acceleration of etch selectivity for self-aligned contact

1995-08-17

1998-09-08

Tsai, Jey

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438683, 438705, 438784, H01L 21461

Patent

active

058045066

ABSTRACT:
A method of fabricating an integrated circuit on a semiconductor substrate is provided including the steps of forming a tungsten silicide conductor structure having a nitride encapsulating layer on the substrate and disposing a doped nonconducting layer over the conductor structure. A self-aligned contact etch is performed wherein the etch is a selective etch of the conductor structure and the nonconducting layer. The selective etch preferentially removes material forming the nonconducting layer rather than material forming the conductor structure. The semiconductor layer is preferably doped with germanium but may also be doped with phosphorous or other known dopants. A germanium concentration of 5% to 25% provides the preferred increased selectivity of the etch. The nonconducting layer can be formed of SG, BPSG, BSG, PSG and TEOS. Transistor regions are formed in the substrate in the vicinity of the tungsten silicide structure and electrical contacts are electrically coupled to the transistor regions by way of openings provided with the selective etch.

REFERENCES:
patent: 5324974 (1994-06-01), Liao
patent: 5571733 (1996-11-01), Wu et al.

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