Input/output buffer system

Details Input/output buffer system Input/output buffer system

1987-03-09

1989-06-13

Shaw, Gareth D.

Boots, shoes, and leggings

3642397, 3642419, G06F 1300

Patent

active

048397911

ABSTRACT:
An input/output buffer system includes: a buffer memory connected between a main memory and an input/output processing unit having a plurality of physical channels, the buffer memory comprising an address area and a data area, the address and data areas being assigned to current physical channels; a register for storing start positions and capacities of the areas to be assigned to the physical channels of the buffer memory and information in units of physical channels, the information representing relative values of data write and read positions of the buffer memory with respect to the start positions of the areas; a combination of a firmware write bus, a firmware channel number register and a selector for presenting in the register the start positions and capacities of the areas assigned to the physical channels of the buffer memory once when the input/output system is started up or modified; and logic circuits for generating the write and read position signals for the buffer memory on the basis of the information stored in the register and for supplying the signals to the buffer memory.

REFERENCES:
patent: 4056843 (1977-11-01), Bishop et al.
patent: 4126897 (1978-11-01), Capowski et al.
patent: 4258418 (1981-03-01), Heath et al.
patent: 4407016 (1983-09-01), Bayliss et al.
patent: 4598357 (1986-07-01), Swenson et al.

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