Acceleration of convergence rate with verified bits in turbo...

Details Acceleration of convergence rate with verified bits in turbo... Acceleration of convergence rate with verified bits in turbo...

2005-09-27

2005-09-27

Chase, Shelly (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S792000

Reexamination Certificate

active

06950975

ABSTRACT:
System and method for accelerating the convergence rate of turbo decoding by verifying bits in data frames whose CRC shows no bit errors. Verified bits are translated to bound nodes on a trellis of nodes representing a sequence of bits of the encoded code block. Verification of all bits signals a stop condition and decoding iterations can be terminated. Further, state transition metrics are limited when a node is adjacent to a bound node, allowing for acceleration of convergence by elimination of impossible state transitions. Also disclosed is a scheme to detect bit errors when the code block contains unframed data or partial data frames. This bit error detection scheme uses a recursive encoder to establish end node status. The end node state determination accelerates convergence rate recognition when incorporated with other stop conditions.

REFERENCES:
patent: 6014411 (2000-01-01), Wang
patent: 6028897 (2000-02-01), Wang
patent: 6044116 (2000-03-01), Wang
patent: 6182261 (2001-01-01), Haller et al.
patent: 6252917 (2001-06-01), Freeman
patent: 6298463 (2001-10-01), Bingeman et al.
patent: 6675342 (2004-01-01), Yagyu

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