Accelerated error detection in a bus bridge circuit

Details Accelerated error detection in a bus bridge circuit Accelerated error detection in a bus bridge circuit

2002-03-28

2004-07-20

Huynh, Kim (Department: 2182)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S313000, C710S107000, C710S036000

Reexamination Certificate

active

06766405

ABSTRACT:

FIELD OF THE INVENTION
The present invention is concerned with computer systems, and is more particularly concerned with error detection by bus bridge circuits in computer systems.
BACKGROUND OF THE INVENTION
FIG. 1
is a block diagram of a typical computer system which employs bus bridge circuits (“bus bridges” or “bridges”) to provide interconnections between buses. Reference numeral
10
generally indicates the computer system. The computer system
10
includes a processor
12
connected via a system bus
14
to a system memory
16
. A host bridge
18
connects the system bus
14
to a first PCI (Peripheral Component Interconnect) bus
20
. A first PCI/PCI bridge
22
connects the first PCI bus
20
to a second PCI bus
24
. A second PCI/PCI bridge
26
connects the second PCI bus
24
to a third PCI bus
28
. I/O (input/output) adapters
30
are connected to the third PCI bus
28
.
A third PCI/PCI bridge
32
connects the second PCI bus
24
to a fourth PCI bus
34
. I/O adapters
36
are connected to the fourth PCI bus
34
. A fourth PCI/PCI bridge
38
connects the first PCI bus
20
to a fifth PCI bus
40
. I/O adapters
42
are connected to the fifth PCI bus
40
.
FIG. 2
shows additional details of the portion of
FIG. 1
that is concerned with the fourth PCI/PCI bridge
38
and the fifth PCI bus
40
. In particular,
FIG. 2
shows that the fourth PCI/PCI bridge
38
stores base address data
44
, limit address data
46
, secondary bus number data
48
, and subordinate bus number data
50
. As will be appreciated by those who are skilled in the art, corresponding data is also stored in the first PCI/PCI bridge
22
, the second PCI/PCI bridge
26
and the third PCI/PCI bridge
32
. In accordance with conventional practice in connection with the well-known PCI protocol, the base address data
44
and the limit address data
46
define a range of addresses to which request commands may be directed. Also in accordance with conventional practice, the secondary bus number data
48
and the subordinate bus number data
50
together define a range of bus numbers to which completions may be directed.
The well-known PCI bus protocol is an industry standard administered by the PCI Special Interest Group. Also available from PCI Special Interest Group for a fee is information regarding a recent extension of the PCI protocol, referred to as “PCI-X” and described in “PCI-X Addendum PCI Local Bus Specification Revision 1.0a Jul. 24, 2000”.
One new feature provided in PCI-X is known as the “split operation”. To briefly illustrate a split operation in the context of a read command, a requesting device (“requester”) issues a read command, and the target device (“completer”) responds with a split response. The completer later issues a split completion to provide the data originally requested by the requester. The split operation feature was added to save bandwidth on the PCI bus by avoiding retries.
FIG. 3
is a flow chart that illustrates performance in accordance with conventional practices of a split read operation in a case where a bridge is positioned between the requesting device and the ultimate target.
The process of
FIG. 3
starts at
52
, and proceeds to block
54
. At block
54
the bridge receives a read command from the requester. The received command includes a PCI address that identifies the target, and an “attribute” which indicates the return address (bus number) for the requester. Following block
54
is block
56
. At block
56
the bridge tests the PCI address received at block
54
against the address range defined by the base address data and the limit address data stored in the bridge to determine whether the read command is properly routable by the bridge. Assuming that the received PCI address is proper, block
58
then follows. At block
58
the bridge accepts the read command. Then, at block
60
, the bridge issues a split response to the requester.
Following block
60
is block
62
. At block
62
the bridge issues a read command on its other bus, passing along the PCI address and the attribute which were received at block
54
. The bridge then receives a split response from the completer (block
54
). After a certain period of time the bridge then receives a split completion from the completer. The split completion includes an address, i.e. a bus number, used to route the completion back to the requester. Following block
66
is decision block
68
. At decision block
68
the bridge determines whether the bus number included in the split completion matches the range of bus numbers supported by the bridge (i.e., the range of bus numbers defined by the secondary bus number data and the subordinate bus number data). If the bus number does match the supported range, then the bridge completes the read operation by transmitting the split completion to the requester (block
70
) and the process ends (
72
).
If a negative determination is made at decision block
68
, i.e. if the bus number received in the split completion does not match the range of bus numbers supported by the bridge, then block
74
follows decision block
68
. At block
74
the bridge ignores (master aborts) the split completion and the process ends (
72
).
The path through block
74
, leading to aborting of the split completion, may occur if the attribute originally provided by the requester was incorrect. This, in turn, may result from corruption of data in the requester, or reassignment of bus numbers by the host without the requester having been properly updated.
The present inventors have recognized certain problems that arise in connection with the conventional split-operation handling process of
FIG. 3
, and particularly with the aborting of the split completion at block
74
. Specifically, the aborting of the split completion leads the completer to issue a general error message which does not (cannot) identify the requester, which is likely the source of the bad bus number. As a result, the system may be unable to identify the source of the malfunction, and may be prevented from making a recovery from the error condition. Furthermore, upon the issuance of the split response at block
60
, the requester may lock resources, such as a buffer in which the desired data is to be written. Also, the bridge may lock a resource, such as a register for storing state information, upon receipt of the split response at block
64
. Both the locked resources at the requester and the locked resources at the bridge may remain locked indefinitely upon aborting of the split completion.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a method of handling a split operation at a bus bridge is provided. The inventive method includes receiving at the bus bridge a read or write command from a requesting device, where the command includes a bus number for routing a completion of the command. The inventive method further includes comparing the bus number received from the requesting device with the return route bus number range of the bus bridge, issuing a split response to the requesting device if the bus number matches the return route bus number range of the bus bridge, and aborting the command if the bus number does not match the return route bus number range of the bus bridge.
In at least one embodiment, the read or write command may be received at the bus bridge via a PCI-X bus. The requesting device may be an I/O adapter.
According to a second aspect of the invention, a computer system is provided. The inventive computer system includes a requesting device connected to a first bus, a completing device connected to a second bus, and a bus bridge interconnecting the first bus and the second bus. The bus bridge is operative to receive a read or write command from the requesting device, where the command includes a bus number for routing a completion of the command. The bus bridge is further operative to (a) compare the bus number with the return route bus number range of the bus bridge, (b) issue a split response to the requesting device if the bus number matches the return route bus nu

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