Accelerated data switching on symmetric multiprocessor...

Details Accelerated data switching on symmetric multiprocessor... Accelerated data switching on symmetric multiprocessor...

2004-08-25

2010-11-23

Ton, Dang T (Department: 2475)

Electrical computers and digital data processing systems: input/

Intrasystem connection

System configuring

C370S360000, C710S001000, C711S154000

Reexamination Certificate

active

07840731

ABSTRACT:
A router that includes a plurality of processors (SMPs) where there is “affinity” between particular processors and particular interfaces: Each of the router's interfaces are assigned to one of the processors. A packet arriving at a particular interface will be handled by the processor having an affinity to that particular interface. If the packet's egress is on an interface assigned to the same processor, then the output process will also be handled by that processor. If the egress interface has an affinity to a different processor, then the packet is handed over to the other processor for egress. The data structures that must be retrieved from memory to handle a packet are often associated with the interfaces through which the packet passes. Thus, having a particular processor handle all the packets that pass through a particular interface insures that the data structures needed to handle the packets will more likely be stored in the processor's cache and less likely be the object of inter-processor lock contention.

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