Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization
Patent
1996-02-05
1998-06-09
Westin, Edward P.
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Signal level or switching threshold stabilization
326 83, 326 58, H03K 1716, H03K 1900
Patent
active
057640777
ABSTRACT:
An output buffer includes a pair of P-channel transistors and two cascode pull-down N-channel transistors to drive an output node. The output pull-up transistor has the gate thereof connected through a P-channel control transistor to an input driving signal. The control signal is isolated from the output node by a P-channel transistor which only conducts during overvoltage conditions. During normal operation, the control transistor is maintained in a conductive state to allow the gate of the output pull-up transistor to be pulled high and low. During an overvoltage condition, the P-channel transistor connected between the output node and the control transistor is turned on in order to effectively turn off the control transistor. The P-channel transistors in the output buffer are floating well-type transistors with the wells thereof tied to a switched voltage that is either the supply voltage during the normal operating mode or the output node during overvoltage conditions.
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Andresen Bernhard Hans
Edmonson Daniel
Brady Wade James
Donaldson Richard L.
Holland Robby T.
Roseen Richard
Texas Instruments Incorporated
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