4-level logic decoder

Details 4-level logic decoder 4-level logic decoder

2006-07-21

2009-06-23

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Three or more active levels

With conversion

C326S093000

Reexamination Certificate

active

07550997

ABSTRACT:
The present invention relates to a 4-level logic decoder for decoding n 4-level input data signals into n 2-bit signals. The 4-level logic decoder comprises n decoding circuits with each decoding circuit comprising comparison circuitries for comparing the 4-level input data signal with a clock signal and a one-bit data signal. In dependence upon the comparison results signals are provided to a decode logic circuit, which are indicative of a data bit value of the 4-level input data signal representing one of the clock signal, the one-bit data signal, and static values of the 4-level input data signal. In dependence upon the signals the decode logic circuit generates then a 2-bit output data signal. The 4-level logic decoder is easily implemented using simple circuit of logic components, which allow modeling using an HDL.

REFERENCES:
patent: 6711218 (2004-03-01), Dent
patent: 7260155 (2007-08-01), Stonick et al.
Kazutaka, Taniguchi “Four-Valued Dynamic Encoder and Decoder Circuits for CMOS Multivalued Logic Systems” IEICE Transactions on Electronics, Electronics Society, Tokyo, JP, vol. E75-C, No. 10, Oct. 1, 1992, pp. 1275-1280.

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