3D polysilicon ROM and method of fabrication thereof

Details 3D polysilicon ROM and method of fabrication thereof 3D polysilicon ROM and method of fabrication thereof

2005-10-04

2005-10-04

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S401000, C438S257000

Reexamination Certificate

active

06952038

ABSTRACT:
A 3D polysilicon ROM including an isolated SiO2layer on a silicon substrate, and an N+ polysilicon layer on the isolated SiO2layer. The N+ polysilicon layer is further defined by a plurality of parallel, separate word lines. A first oxide layer fills the space between the word lines. A dielectric layer is deposited on the word lines and the first oxide layer. A P− polysilicon layer is deposited on the dielectric layer and further defines a plurality of parallel, separate bit lines. The bit lines overlap the word lines, from a top view, to form an approximately cross shape. The neck structure may be individually formed between the P− and N+ polysilicon layers by wet etching the dielectric layer with dilute hydrofluoric acid. A second oxide layer fills the space between the bit lines and is on the word lines and the first oxide layer.

REFERENCES:
patent: 6794280 (2004-09-01), Chang

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