Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2008-08-29
2011-10-04
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S118000
Reexamination Certificate
active
08032854
ABSTRACT:
A 3-stack floorplan for a floating point unit includes: an aligner located in the center of the floating point unit; a frontend located directly above the aligner; a multiplier located directly below the frontend and next to the aligner; an adder located directly next to the multiplier and directly below the aligner; a normalizer located directly above the adder; and a rounder located directly above the normalizer.
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E. Schwarz, “Binary Floating-Point Unit Design: the Fused Multiply-Add Dataflow,” High Performance Energy-Efficient Microprocessor Design, 2006, pp. 189-208, Springer Verlag, New York.
Y-H. Chan, et al., “4GHz+ Low-Latency Fixed-Point and Binary Floating-Point Execution Units for the POWER6 Processor,” Solid-State Circuits Conference, ISSCC, Digest of Technical Papers, 2006, pp. 1728-1734, IEEE International, China.
S.R. Carlough, et al., “IBM POWER6 Accelerators: VMX and DFU,” IBM Journal of Research and Development, Nov. 2007, pp. 663-684, vol. 51 No. 6, International Business Machines Corporation, New York.
M. Kroener et al., “P6 Binary Floating-Point Unit,” [online]; [retrieved on Aug. 15, 2008]; retrieved from the Internet http://www.lirmm.fr/arith18/papers/daotrongs-1-p6bfu.pdf.
Boersma Maarten
Kroener Michael
Leber Petra
Mueller Silvia M.
Preiss Jochen
Bowers Brandon
Cantor & Colburn LLP
Chiang Jack
International Business Machines - Corporation
Talpis Matthew
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