3-D integrated circuit system and method

Details 3-D integrated circuit system and method 3-D integrated circuit system and method

2011-08-16

2011-08-16

Ngo, Ngan (Department: 2893)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

Amorphous semiconductor

C438S486000, C438S489000, C438S799000, C438S478000, C257SE21028, C257SE21134, C257SE21347

Reexamination Certificate

active

07998846

ABSTRACT:
A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.

REFERENCES:
patent: 6787825 (2004-09-01), Gudesen et al.
patent: 2001/0002324 (2001-05-01), Maekawa et al.
patent: 2002/0068421 (2002-06-01), Yamazaki et al.
patent: 2006/0063351 (2006-03-01), Jain
patent: 2007/0141858 (2007-06-01), Gu

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