2-bit mask ROM device and fabrication method thereof

Details 2-bit mask ROM device and fabrication method thereof 2-bit mask ROM device and fabrication method thereof

2002-08-28

2003-07-08

Ho, Hoai (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S391000, C438S278000

Reexamination Certificate

active

06590266

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a mask read-only memory (ROM) device and a fabrication method thereof. More particularly, the present invention relates to a two-bit mask ROM device and a fabrication method thereof.
2. Description of Related Art
Mask ROM device is a very fundamental type of read-only memory devices, in which a photomask layer is used to define a connection between a metal line and a memory cell or an ion implantation process is used to adjust the threshold voltage to achieve the “on” and “off” state of the memory cell. When there are changes in the product of a mask ROM device, no dramatic modification is required by the manufacturing process. Only one set of photomask needs to be changed. Therefore, the mask ROM device is suitable for mass production. Actually, a portion of the manufacturing of the mask ROM device can be completed first. The programming of the device can be quickly performed soon after an order is placed to move up the delivery/shipping date.
Currently the two-bit mask ROM device is actively being developed. A two-bit mask ROM device obviously is a memory device wherein two bit of data are stored per a single cell. The structure of this type of memory device is described as follow.
FIG. 1
is a schematic cross sectional view of a conventional two bit mask read only memory (ROM) device.
Referring to
FIG. 1
, a conventional two bit mask read only memory device comprises a substrate
10
, a gate structure
16
, a two-bit code region
20
, a buried drain region
18
, an insulation layer
22
and a word line
24
.
The gate structure
16
is disposed on a part of the substrate
10
. The gate structure
16
comprises a gate conductive layer
14
and a gate oxide layer
12
disposed under the gate conductive layer
14
. The buried drain region
18
is configured in the substrate
100
beside both sides of the gate structure
16
.
Further, a two-bit code region
20
is configured in the substrate
10
besides both sides of the gate structure
16
. The two-bit code region
20
that comprises code ions implanted therein corresponds to a logic state of “1”, whereas the two-bit code region
20
that comprises no code ions implanted therein corresponds to a logic state of “0”.
However, the buried drain region and the two-bit coding region of a conventional two-bit mask ROM device are connected together. Junction leakage is thus easily occurred. Moreover, the second bit effect is easily generated. Since the memory cell of a conventional mask ROM device is easily interfered by junction leakage of the neighboring memory cells and the second bit effect is often generated, the operation window is thus smaller for a conventional memory device.
SUMMARY OF INVENTION
According to the present invention, a two-bit mask ROM device and a fabrication method thereof are provided to eliminate the second bit effect in a two-bit mask ROM device.
The present invention further provides a two-bit mask ROM device and a fabrication method thereof, wherein an interference to the two-bit memory cell by junction leakage of other memory cells is prevented.
In accordance to the present invention, a two-bit mask ROM device is provided, which includes a substrate, a gate structure, a two-bit code region and at least a spacer, a buried drain region, a doped region, an insulation layer and a word line. The gate structure is disposed on a part of the substrate, wherein the gate structure includes a gate conductive layer and a gate oxide layer. The two-bit code region is disposed in the substrate beside both sides of the gate structure, wherein the two-bit code region having code ions implanted therein corresponds to a logic state of “1”, while the two-bit code region having no code ions implanted therein corresponds to a logic state of “0”. Further, a spacer is disposed on both sides of the gate structure and a buried drain region is configured in the substrate beside both sides of the spacer. A doped region is configured between the buried drain region and the 2 bit-code code region, wherein the doped region almost completely encloses the two-bit code region. In the present invention, the dopant type of the doped region is different form that of the of the two-bit code region. Further, the dopant concentration of the doped region is higher than the dopant concentration in the two-bit code region. Additionally, the insulation layer is disposed above the buried drain region, and the word line is disposed on the gate structures along a same row, wherein the word line includes a polysilicon layer and a metal silicide layer disposed on the polysoilicon layer.
The present invention provides a fabrication method for a two-bit mask ROM device, wherein a gate structure is formed on a substrate, and the gate structure comprises a gate conductive layer and a gate oxide layer underlying the gate conductive layer. Thereafter, a patterned photoresist layer is formed on the substrate, exposing a two-bit code region. A tilted code implantation is then performed to implant code ions in the 2-bit code region, using the photoresist layer as a code implantation mask. Thereafter, a first ion implantation is performed to form a doped region in the substrate using this photoresist layer as a mask, wherein the, dopant type of the doped region is different from that of the 2-bit code region. Moreover, the dopant concentration in the doped region is higher than the dopant concentration in the 2-bit code region. Thereafter, the photoresist layer is removed. At least one spacer is formed on the side of the gate structure. Using the gate structure and the spacer as an ion implantation mask, a second ion implantation is performed to form a buried drain region in the substrate beside the side of the spacer. A plurality of 2-bit code memory cells is thus formed. In each 2-bit code memory cell, the presence of the code ions implanted in the memory cell corresponds to a logic state of “1”, while the absence of the code ions implanted in the memory cell corresponds to a logic state of “0”. Further, an insulation layer is formed above the buried drain region, and a word line is formed above gate structures along a same row. The doped region of the present invention, after being subjected to a series of thermal process, almost completely encloses the two-bit code region.
According to the 2-bit mask ROM device and the fabrication method thereof of the present invention, the 2-bit code region is almost completely enclosed by the doped region. Interference between memory cells can be prevented.
The 2-bit code region of the 2-bit mask ROM device of the present invention is almost completely enclosed by a doped region having a dopant type different from that of the 2-bit code region and a dopant concentration higher than that of the 2-bit code region. Therefore, the second bit effect of the 2-bit mask ROM device can be eliminated by drain induced barrier lowering.
Since the two-bit memory cells of the 2-bit mask ROM device of the present invention do not interfered with each other, and the second-bit effect of the 2-bit mask ROM device can be eliminated by drain induced barrier lowering, the operational margin of the memory device is increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6087699 (2000-07-01), Wann et al.
patent: 6458642 (2002-10-01), Yeh et al.

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