1P1N 2T gain cell

Details 1P1N 2T gain cell 1P1N 2T gain cell

2006-10-17

2006-10-17

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Continuous cells

C365S102000

Reexamination Certificate

active

07123500

ABSTRACT:
A two-transistor DRAM cell includes an NMOS device and a PMOS device coupled to the NMOS device.

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Ikeda, N., et al., “A Novel Logic Compatible Gain Cell with two Transistors and one Capacitor,” ULSI R&D Laboratories, LSI Business & Technology Group.
C.N.C., Sony Corporation, Japan, 2000 Symposium on VSLI Technology Digest of Technical Papers, IEEE, pp. 168-169.

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