Analog-digital converter optimized for high speed operation

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

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C341S155000

Reexamination Certificate

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07119729

ABSTRACT:
A first analog-digital converter circuit in a preceding stage converts an input analog signal into a digital value and retrieves the higher 4 bits. A second analog-digital converter circuit in a subsequent stage converts an input analog signal into a digital value and retrieves 3 bits including the 5th through 6th highest bits and a redundant bit, 3 bits including the 7th through 8th highest bits and a redundant bit, and 3 bits including the 9th through 10th highest bits and a redundant bit. Thus, the number of bits produced by conversion by the second analog-digital converter circuit in the subsequent stage of a cyclic type is configured to be smaller than the number of bits produced by conversion by the first analog-digital converter circuit in the preceding stage.

REFERENCES:
patent: 6195032 (2001-02-01), Watson et al.
patent: 6366230 (2002-04-01), Zhang et al.
patent: 6396429 (2002-05-01), Singer et al.
patent: 6914550 (2005-07-01), Cai
patent: 6977604 (2005-12-01), Wada et al.
patent: 6987477 (2006-01-01), Aude
patent: 7002507 (2006-02-01), Kobayashi et al.
patent: 2003/0006926 (2003-01-01), Nikai et al.
patent: 4-26229 (1992-01-01), None

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