Method and apparatus for controlling column select lines in a sy

Details Method and apparatus for controlling column select lines in a sy Method and apparatus for controlling column select lines in a sy

1998-03-31

2000-04-25

Nelms, David

Static information storage and retrieval

Read/write circuit

Signals

36523006, 365233, G11C 700

Patent

active

060551941

ABSTRACT:
A column select line control circuit for a synchronous semiconductor memory device increases the time margin for writing input data to memory cells in prefetch mode by delaying the disablement of the column select lines during a write operation, thereby extending the time for writing data to the cells. The control circuit includes a column select line control circuit that generates enable and disable signals in response to an internal clock signal, and a column decoder that enables and disables a column select line in response to the enable and disable signals. In pipeline mode, the column select line control circuit generates the disable signal by delaying the internal clock signal and generates the enable signal by delaying and inverting the internal clock signal. In prefetch mode, the column select line control signal adds an additional delay to both the enable and disable signals, but only during write operations.

REFERENCES:
patent: 5835446 (1998-11-01), Park
patent: 5848024 (1998-12-01), Cho
patent: 5872742 (1999-02-01), Kengeri et al.
patent: 5881017 (1999-03-01), Matsumoto et al.
patent: 5883855 (1999-03-01), Fujita
patent: 5946266 (1999-08-01), Iwamoto et al.
"A 2.5ns Clock Access 250MHz 256Mb SDRAM with a Synchronous Mirror Delay," Takanori Saeki, et al., 1996 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 374-375.

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