Method to decrease capacitance depletion, for a DRAM capacitor,

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438255, 438254, 438398, 438397, 438256, H01L 218234

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active

061658308

ABSTRACT:
A process for creating a DRAM capacitor structure, featuring a doped polysilicon layer, overlying a crown shaped storage node electrode, has been developed. The process features the use of an HSG silicon layer, on a doped amorphous silicon, storage node shape, with the HSG silicon layer supplying increased surface area, and thus increased capacitance, for the DRAM capacitor. A doped polysilicon layer, selectively deposited on the underlying HSG silicon layer, supplies additional dopant to the HSG silicon layer, residing on the doped amorphous silicon, storage node shape, thus minimizing a capacitance depletion phenomena, that can be present with lightly doped storage node structures.

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