Static random access memory device having a memory cell array re

Details Static random access memory device having a memory cell array re Static random access memory device having a memory cell array re

1997-06-26

2000-09-12

Monin, Jr., Donald L.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257903, 438154, 438199, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

061181587

ABSTRACT:
A static random access memory (SRAM) device having an improved degree of integration. The SRAM device has a cell array region in which a unit cell is arranged in a matrix. The unit cell includes a first NMOS inverter including a first NMOS driver transistor and a first NMOS access transistor, a second NMOS inverter including a second NMOS driver transistor and a second NMOS access transistor, a first CMOS inverter including the first NMOS driver transistor and a first PMOS load transistor, and a second CMOS inverter including the second NMOS driver transistor and a second PMOS load transistor, wherein the first and second NMOS inverters, and the first and second CMOS inverters are respectively connected by a flip-flop, and a pick-up region for applying a predetermined bias voltage to the memory cell array region formed in a semiconductor substrate is included in the memory cell array region.

REFERENCES:
patent: 5072286 (1991-12-01), Minami et al.
patent: 5854497 (1998-12-01), Hiramoto et al.
patent: 5910674 (1999-06-01), Kasai

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