Method of fabricating CMOS transistors with self-aligned planari

Details Method of fabricating CMOS transistors with self-aligned planari Method of fabricating CMOS transistors with self-aligned planari

1998-01-16

2000-12-05

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438217, 438228, 438231, H01L 28238

Patent

active

061565911

ABSTRACT:
The present invention discloses a method of forming CMOS transistors with self-aligned planarization twin-well by using fewer mask counts. After a silicon nitride layer is formed over a pad oxide layer on a semiconductor substrate, an n-well region is defined by implanting a high energy dose phosphorous in the semiconductor substrate. When the photoresist layer used for defining the n-well is stripped, a high energy and low dose blanket boron is implanted under the n-well region in the semiconductor substrate. Next, both the silicon nitride layer and the pad oxide layer are removed. A high temperature steam oxidation process is then performed to remove the crystalline defects, and the in-situ high temperature long time anneal is done to form a deep twin-well. A thick pad oxide layer formed by the high temperature steam oxidation is then removed, and an active region is defined followed by a standard oxidation process to grow a thick field oxide region. After a phosphorous punch-through stopping implant is performed in the semiconductor substrate for the PMOSFET, another high energy and low dose blanket boron is implanted in a semiconductor substrate for increasing the threshold voltage of the NMOSFET field oxide device. Both the threshold voltages of the buried channel PMOSFET and surface channel NMOSFET are then adjusted by a low energy and low dose blanket BF.sub.2 implant. Finally, the standard processes can be employed for fabricating the CMOS transistors.

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