Method of etching SiO.sub.2 dielectric layers using chemical mec

Details Method of etching SiO.sub.2 dielectric layers using chemical mec Method of etching SiO.sub.2 dielectric layers using chemical mec

1991-07-29

1992-12-08

Hearn, Brian E.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

437228, 437235, H01L 2100

Patent

active

051694913

ABSTRACT:
A method of planarizing SiO.sub.2 containing dielectric in semiconductor wafer processing comprising: a) providing a layer of undoped SiO.sub.2 atop a wafer; b) depositing a layer of borophosphosilicate glass atop the layer of undoped SiO.sub.2 ; and c) chemical mechanical polishing the borophosphosilicate glass layer selectively relative to the underlying layer of undoped SiO.sub.2 layer and using the layer of undoped SiO.sub.2 as an effective chemical mechanical polishing end-point etch stop to prevent further etching of the borophosphosilicate glass and produce a substantially planar upper wafer surface of dielectric.

REFERENCES:
patent: 4671851 (1987-06-01), Beyer et al.
patent: 4789560 (1988-12-01), Yen
patent: 4944836 (1990-07-01), Beyer et al.
patent: 4956313 (1990-09-01), Cote et al.
patent: 5096854 (1992-03-01), Saito et al.
Translation of Hirobe et al., JP 61-194748.
K. D. Beyer et al., "Glass Planarization by Stop-Layer Polishing", IBM Technical Disclosure Bulletin, vol. 27, No. 8, Jan. '85, pp. 4700-4701.
Wolf, "Silicon Processing for the VLSI Era", vol. 2--Process Integration, Lattice Press, pp. 199-239.

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